spi_hw.c File Reference

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Functions

void spi_hw_init ()
uns8 spi_hw_master_receive ()
void spi_hw_master_transmit (uns8 data)
void spi_hw_setup_io ()

Function Documentation

void spi_hw_init (  ) 

00099                    {
00100     
00101     #ifdef SPI_HW_CLK_IDLE_IS_HIGH
00102         set_bit(sspcon1, CKP);
00103     #else   
00104         // for 0,0 mode - mrf24j40 needs this
00105         clear_bit(sspcon1, CKP);
00106     #endif
00107     #ifdef SPI_HW_MASTER_MODE   
00108 
00109         set_bit(sspstat, SMP);  // from tim
00110     #else
00111         clear_bit(sspstat, SMP);    // smp must be cleared in slave mode
00112     #endif  
00113     
00114     #ifdef SPI_HW_TRANSMIT_ON_IDLE_TO_ACT
00115         clear_bit(sspstat, CKE);
00116     #else
00117         // need this for mrf24j40
00118         // for 0,0 mode
00119         set_bit(sspstat, CKE);
00120     #endif  
00121     set_bit(sspcon1, SSPEN);    // enable mssp serial port
00122 }

uns8 spi_hw_master_receive (  ) 

00141                              {
00142 
00143     spi_hw_master_transmit(0x00);   // dummy transmit to get something back
00144     return sspbuf;
00145     
00146 }

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void spi_hw_master_transmit ( uns8  data  ) 

00126                                        {
00127 
00128     clear_bit(pir1, SSPIF);
00129     // Try and send, if we have something already sending, try again
00130     do {
00131         clear_bit(sspcon1, WCOL);
00132         sspbuf = data;
00133     } while (test_bit(sspcon1, WCOL));
00134     
00135     // Wait here while we transmit
00136     // Note that we will hang here if we don't have SPI setup properly
00137     // or we're running under the simulator
00138     while (!test_bit(pir1, SSPIF)) {}
00139 }

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void spi_hw_setup_io (  ) 

00040                        {
00041 
00042 #ifndef _PIC18F14K50
00043     make_output(PORTC, 5);
00044     make_input(PORTC, 4);
00045 #else
00046 #endif
00047 
00048 #ifdef SPI_HW_MASTER_MODE
00049     
00050     #ifndef _PIC18F14K50
00051     #else
00052         make_output(PORTC, 3);
00053     #endif
00054         
00055     clear_bit(sspcon1, SSPM3);
00056     clear_bit(sspcon1, SSPM2);
00057     #ifdef SPI_HW_MASTER_CLOCK_TMR2_DIV_2
00058         set_bit(sspcon1, SSPM1);
00059         set_bit(sspcon1, SSPM0);
00060     #endif
00061     #ifdef SPI_HW_MASTER_CLOCK_FOSC_DIV_64
00062         set_bit  (sspcon1, SSPM1);
00063         clear_bit(sspcon1, SSPM0);
00064     #endif
00065     #ifdef SPI_HW_MASTER_CLOCK_FOSC_DIV_16
00066         clear_bit(sspcon1, SSPM1);
00067         set_bit  (sspcon1, SSPM0);
00068     #endif
00069     #ifdef SPI_HW_MASTER_CLOCK_FOSC_DIV_4
00070         clear_bit(sspcon1, SSPM1);
00071         clear_bit(sspcon1, SSPM0);
00072     #endif
00073 #else
00074     // Slave mode
00075     #ifndef _PIC18F14K50
00076         make_input(PORTC, 3);   // sck
00077     #else
00078         make_input(PORTB, 6);   // sck
00079         make_output(PORTC, 7);  // sdo
00080     #endif
00081     clear_bit(sspcon1, SSPM3);
00082     set_bit  (sspcon1, SSPM2);
00083     clear_bit(sspcon1, SSPM1);
00084     #ifdef SPI_HW_USE_SS
00085         #ifndef _PIC18F14K50
00086             make_input(PORTA, 5);   // SS
00087         #else
00088             make_input(PORTC, 6);   // SS
00089         #endif
00090         clear_bit(sspcon1, SSPM0);
00091     #else
00092         set_bit(sspcon1, SSPM0);
00093     #endif
00094 #endif
00095 
00096 }   


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