Routines to access the AR1000 FM radio chip. More...
Go to the source code of this file.
ITS networking routines - common to mode 1 and 2.
#define AR1000_CHIP_ID 28 |
Chip id - 0x1000 for RDS version, 0x1010 for non-rds version
#define AR1000_DEV_ADDR 0b00100000 |
#define AR1000_DEV_ID 27 |
#define AR1000_R0 0 |
#define AR1000_R1 1 |
#define AR1000_R10 10 |
#define AR1000_R11 11 |
#define AR1000_R13 13 |
GPIO controls in this register
#define AR1000_R14 14 |
#define AR1000_R15 15 |
#define AR1000_R2 2 |
#define AR1000_R3 3 |
#define AR1000_RBS 20 |
#define AR1000_RDS_1 21 |
#define AR1000_RDS_2 22 |
#define AR1000_RDS_3 23 |
#define AR1000_RDS_4 24 |
#define AR1000_RDS_5 25 |
#define AR1000_RDS_6 26 |
#define AR1000_RSSI 18 |
#define ar1000_setup | ( | ) | ar1000_setup_io() |
define so as not to break existing code with new naming standard
#define AR1000_STATUS 19 |
#define DEV_ID_MFID_0 0 |
MFID (12 bits 5B1) bit 0
#define DEV_ID_MFID_1 1 |
MFID (12 bits 5B1) bit 1
#define DEV_ID_MFID_10 10 |
MFID (12 bits 5B1) bit 10
#define DEV_ID_MFID_11 11 |
MFID (12 bits 5B1) bit 11
#define DEV_ID_MFID_2 2 |
MFID (12 bits 5B1) bit 2
#define DEV_ID_MFID_3 3 |
MFID (12 bits 5B1) bit 3
#define DEV_ID_MFID_4 4 |
MFID (12 bits 5B1) bit 4
#define DEV_ID_MFID_5 5 |
MFID (12 bits 5B1) bit 5
#define DEV_ID_MFID_6 6 |
MFID (12 bits 5B1) bit 6
#define DEV_ID_MFID_7 7 |
MFID (12 bits 5B1) bit 7
#define DEV_ID_MFID_8 8 |
MFID (12 bits 5B1) bit 8
#define DEV_ID_MFID_9 9 |
MFID (12 bits 5B1) bit 9
#define DEV_ID_VERSION_0 12 |
Version of FM radio bit 0
#define DEV_ID_VERSION_1 13 |
Version of FM radio bit 1
#define DEV_ID_VERSION_2 14 |
Version of FM radio bit 2
#define DEV_ID_VERSION_3 15 |
Version of FM radio bit 3
#define R0_ENABLE 0 |
#define R0_INT_OSC_EN 15 |
#define R10_SEEK_WRAP_ENABLE 3 |
Seek wrap enable
#define R11_AFC_HIGH_SIDE_b1 2 |
High side control bits
#define R11_AFC_HIGH_SIDE_b2 0 |
#define R11_AFC_INJECTION_CONTROL 15 |
AFC injection control
#define R11_HILO_SIDE 15 |
#define R13_GPIO1_0 0 |
#define R13_GPIO1_1 1 |
GPIO1- 00-Disable 01-Reserved 10-Output logic 0 11-Output logic 1
#define R13_GPIO2_0 2 |
#define R13_GPIO2_1 3 |
GPIO2- 00-Disable 01-STC or RDS interrupt 10-Output logic 0 11-Output logic 1
#define R13_GPIO3_0 4 |
#define R13_GPIO3_1 5 |
GPIO3- 00-Disable 01-Stereo indication 10-Output logic 0 11-Output logic 1
#define R14_VOL2_0 12 |
Second volume settings (bit 0)
#define R14_VOL2_1 13 |
Second volume settings (bit 1)
#define R14_VOL2_2 14 |
Second volume settings (bit 2)
#define R14_VOL2_3 15 |
Second volume settings (bit 3)
#define R15_RDS_CTRL 0 |
RDS Control mode 0=block mode (RDSR asserted after 4 blocks received, data in blocks may not be correct. RBS1-4 will present the status of each block) 1=group mode (RDSR is asserted after 4 blocks received without any error)
#define R15_RDS_MECC_0 3 |
#define R15_RDS_MECC_1 4 |
RDS Error correction 0x=disable erorr correction 10=2 bit error correction 11=5 bit error correction
#define R15_RDS_STA_EN 5 |
RDS statistic data enable signal
#define R1_DEEMP_SETTING 4 |
De-emphasis 1=75us 0=50us
#define R1_FORCE_MONO 3 |
Force mono
#define R1_HARD_MUTE_ENABLE 1 |
Hard mute enable
#define R1_RDS_ENABLE 13 |
Enable RDS signal
#define R1_RDS_INT_ENABLE 6 |
Enable RDS interrupt
#define R1_SOFT_MUTE_ENABLE 2 |
Soft mute enable
#define R1_STC_INT_ENABLE 5 |
Seek Tune Complete (STC) interrupt enable
#define R2_CHAN_0 0 |
#define R2_CHAN_1 1 |
#define R2_CHAN_2 2 |
#define R2_CHAN_3 3 |
#define R2_CHAN_4 4 |
#define R2_CHAN_5 5 |
#define R2_CHAN_6 6 |
#define R2_CHAN_7 7 |
#define R2_CHAN_8 8 |
#define R2_TUNE_ENABLE 9 |
Tune channel enable
#define R3_BAND_0 11 |
Band control 0=Japan narrow band 76Mhz - 90Mhz 1=Japan wide band 76Mhz - 108Mhz
#define R3_BAND_1 12 |
Band control 0=US/EUROPE 1=Japan
#define R3_SEEK_CHANNEL_SPACING 13 |
Seek channel spacing 1=100k 0=200k
#define R3_SEEK_ENABLE 14 |
Seek enable
#define R3_SEEK_UP 15 |
Seek direction 1=up 0=down
#define R3_SEEKTH_0 0 |
#define R3_SEEKTH_1 1 |
#define R3_SEEKTH_2 2 |
#define R3_SEEKTH_3 3 |
#define R3_SEEKTH_4 4 |
#define R3_SEEKTH_5 5 |
#define R3_SEEKTH_6 6 |
#define R3_VOL_0 7 |
#define R3_VOL_1 8 |
#define R3_VOL_2 9 |
#define R3_VOL_3 10 |
#define STATUS_BIT_2 2 |
Used but unknown function
#define STATUS_CHAN_0 7 |
Current tuned channel bit 0
#define STATUS_CHAN_1 8 |
Current tuned channel bit 1
#define STATUS_CHAN_2 9 |
Current tuned channel bit 2
#define STATUS_CHAN_3 10 |
Current tuned channel bit 3
#define STATUS_CHAN_4 11 |
Current tuned channel bit 4
#define STATUS_CHAN_5 12 |
Current tuned channel bit 5
#define STATUS_CHAN_6 13 |
Current tuned channel bit 6
#define STATUS_CHAN_7 14 |
Current tuned channel bit 7
#define STATUS_CHAN_8 15 |
Current tuned channel bit 8
#define STATUS_RDS_DATA_READY 6 |
RDS data recevied
#define STATUS_SEEK_FAIL 4 |
Seek has failed
#define STATUS_SEEK_TUNE_COMPLETE 5 |
Seek or Tune has completed
#define STATUS_STEREO 3 |
Stereo flag 1=stereo 0=mono
uns8 ar1000_get_register | ( | uns8 | reg | ) |
00056 { 00057 return regs[reg]; 00058 }
void ar1000_init | ( | ) |
00224 { 00225 ar1000_seek_threshold = 0; 00226 for (uns8 count = 1; count < 18; count ++) { 00227 i2c_write_eeprom_16bit(AR1000_DEV_ADDR, count, regs[count]); 00228 } 00229 i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 0, regs[0]); 00230 00231 }
uns16 ar1000_read_register | ( | uns8 | reg | ) |
00071 { 00072 00073 return i2c_read_eeprom_16bit(AR1000_DEV_ADDR, reg); 00074 00075 }
void ar1000_seek | ( | uns16 | frequency, | |
bit | seek_up | |||
) |
00083 { 00084 00085 uns16 r1, r2, r3; 00086 00087 r1 = i2c_read_eeprom_16bit(AR1000_DEV_ADDR, 1); 00088 r2 = i2c_read_eeprom_16bit(AR1000_DEV_ADDR, 2); 00089 r3 = i2c_read_eeprom_16bit(AR1000_DEV_ADDR, 3); 00090 00091 // Set hmute bit 00092 set_bit(r1, R1_HARD_MUTE_ENABLE); 00093 00094 i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 1, r1); 00095 00096 // clear tune bit 00097 clear_bit(r2, R2_TUNE_ENABLE); 00098 00099 // set chan bits r2 to 87.5Mhz 00100 // Means setting the bits to 185 00101 r2 = r2 & 0b1000000000000000; // Mask out tune bits 00102 //r2 = r2 + (frequency - 690); // eg 875 - 690 = 185 for 87.5Mhz 00103 r2 = r2 & ((frequency - 690) << 7); // eg 875 - 690 = 185 for 87.5Mhz 00104 00105 i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 2, r2); 00106 00107 // clear seek bit 00108 clear_bit(r3, R3_SEEK_ENABLE); 00109 i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 3, r3); 00110 00111 // Set SEEK UP/DOWN / SPACE / BAND / SEEKTH 00112 if (seek_up) { 00113 set_bit(r3, R3_SEEK_UP); 00114 } else { 00115 clear_bit(r3, R3_SEEK_UP); 00116 } 00117 set_bit(r3, R3_SEEK_CHANNEL_SPACING); // 100k spacing 00118 clear_bit(r3, R3_BAND_1); // US / EUROPE 00119 00120 r3 = r3 & 0b1111111110000000 + ar1000_seek_threshold; 00121 i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 3, r3); 00122 00123 // Enable SEEK Bit 00124 set_bit(r3, R3_SEEK_ENABLE); 00125 i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 3, r3); 00126 00127 // Wait STC flag (Seek/Tune Complete, in “Status” register) 00128 // Not done yet! not sure which register it is... 00129 00130 // Clear hmute Bit 00131 clear_bit(r1, R1_HARD_MUTE_ENABLE); 00132 i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 1, r1); 00133 // register_values[02] = 0xB480; //set tune to 900kHz 00134 // register_values[03] = 0xA001; //turn off seek, seek up, set threshold to 1 00135 00136 // ar1000calibration(register_values); 00137 00138 // register_values[03] = 0xE001; //turns on seek 00139 00140 // ar1000calibration(register_values); 00141 00142 00143 }
void ar1000_seek2 | ( | ) |
00234 { 00235 // i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 2, 0xb480); 00236 // i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 3, 0xa001); 00237 // i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 3, 0xe001); 00238 //0xF4B9 00239 regs[2] = 0xcd80; //0xB480;// 0xf4b9; //0b1111111000000000; 00240 //ar1000_init(); 00241 regs[3] = 0xa001; 00242 ar1000_init(); 00243 regs[3] = 0xe001; 00244 ar1000_init(); 00245 // register_values[02] = 0xB480; //set tune to 900kHz 00246 // register_values[03] = 0xA001; //turn off seek, seek up, set threshold to 1 00247 00248 // ar1000calibration(register_values); 00249 00250 // register_values[03] = 0xE001; //turns on seek 00251 00252 // ar1000calibration(register_values); 00253 }
void ar1000_seek_more | ( | ) |
00273 { 00274 // i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 2, 0xb480); 00275 // i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 3, 0xa001); 00276 // i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 3, 0xe001); 00277 //0xF4B9 00278 // regs[2] = 0; //0xB480;// 0xf4b9; //0b1111111000000000; 00279 set_bit(regs[2], R2_TUNE_ENABLE); 00280 uns16 channel = i2c_read_eeprom_16bit(AR1000_DEV_ADDR, AR1000_STATUS); 00281 channel = channel >> 7; 00282 serial_print_str(" fr="); 00283 serial_print_int(channel+690); 00284 serial_print_nl(); 00285 //channel = channel << 6; 00286 regs[2] = channel; 00287 set_bit(regs[2], R2_TUNE_ENABLE); 00288 //ar1000_init(); 00289 regs[3] = 0xa005; 00290 ar1000_init(); 00291 regs[3] = 0xe005; 00292 ar1000_init(); 00293 }
void ar1000_set_register | ( | uns8 | reg, | |
uns8 | data | |||
) |
00051 { 00052 regs[reg] = data; 00053 }
void ar1000_set_seek_threshold | ( | uns8 | new_seek_threshold | ) |
00220 { 00221 ar1000_seek_threshold = new_seek_threshold; 00222 }
void ar1000_set_volume | ( | uns8 | volume | ) |
00321 { 00322 00323 uns16 reg, temp; 00324 uns8 vol; 00325 uns16 vol1, vol2; 00326 00327 if (volume > 21) { return; } 00328 vol = vol_lookup[volume]; 00329 vol2 = vol >> 4; 00330 vol1 = vol & 0x0f; 00331 00332 00333 regs[3] = (regs[3] & ~0x0780) | (vol1 << 7); 00334 //write(3, register_values[3]); 00335 00336 regs[14] = (regs[14] & ~0xF000) | (vol2 << 12); 00337 //write(14, register_values[14]); 00338 00339 //serial_print_str(" AR3="); 00340 //serial_print_int_hex_16bit(reg); 00341 //regs[3] = reg; 00342 ar1000_init(); 00343 }
void ar1000_setup_io | ( | ) |
00046 { 00047 i2c_setup(); 00048 }
void ar1000_test | ( | ) |
00255 { 00256 /* serial_print_str("Read 01 = "); 00257 uns16 r1 = i2c_read_eeprom_16bit(AR1000_DEV_ADDR, 1); 00258 serial_print_int_hex_16bit(r1); 00259 serial_print_nl(); 00260 serial_print_str("Write "); 00261 i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 1, 0xabcd); 00262 serial_print_str("Read 01 = "); 00263 r1 = i2c_read_eeprom_16bit(AR1000_DEV_ADDR, 1); 00264 serial_print_int_hex_16bit(r1); 00265 serial_print_nl(); 00266 */ 00267 uns16 r1 = i2c_read_eeprom_16bit(AR1000_DEV_ADDR, 1); 00268 toggle_bit(r1, R1_HARD_MUTE_ENABLE); 00269 i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 1, r1); 00270 00271 }
void ar1000_tune | ( | uns16 | frequency | ) |
00145 { 00146 00147 uns16 r1, r2, r3; 00148 set_bit(regs[3], R3_SEEK_CHANNEL_SPACING); 00149 regs[2] = 0b0000000100111111; 00150 ar1000_init(); 00151 regs[2] = 0b0000001100111111; 00152 00153 ar1000_init(); //a7e0 00154 return; 00155 r1 = i2c_read_eeprom_16bit(AR1000_DEV_ADDR, 1); 00156 r2 = i2c_read_eeprom_16bit(AR1000_DEV_ADDR, 2); 00157 serial_print_str("r2o="); 00158 serial_print_int_hex(r2); 00159 r3 = i2c_read_eeprom_16bit(AR1000_DEV_ADDR, 3); 00160 //1 100111111 000000 00161 // Set hmute bit 00162 set_bit(r1, R1_HARD_MUTE_ENABLE); 00163 i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 1, r1); 00164 00165 00166 // clear tune bit 00167 clear_bit(r2, R2_TUNE_ENABLE); 00168 i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 2, r2); 00169 00170 // clear seek bit 00171 clear_bit(r3, R3_SEEK_ENABLE); 00172 i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 3, r3); 00173 00174 // Set SPACE / BAND / CHAN 00175 set_bit(r3, R3_SEEK_CHANNEL_SPACING); // 100k spacing 00176 clear_bit(r3, R3_BAND_1); // US / EUROPE 00177 i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 3, r3); 00178 00179 // set chan bits r2 to 87.5Mhz 00180 // Means setting the bits to 185 00181 //serial_print_str("f="); 00182 //serial_print_int(frequency); 00183 //serial_print_nl(); 00184 r2 = frequency - 690; 00185 //serial_print_str(" f-690="); 00186 //serial_print_int(r2); 00187 r2 = r2 << 6; 00188 //serial_print_str("tuning to="); 00189 //serial_print_int_hex_16bit(r2); 00190 i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 2, r2); 00191 // 100111100 0000000 00192 // Enable TUNE Bit 00193 set_bit(r2, R2_TUNE_ENABLE); 00194 i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 2, r2); 00195 //1 001111000 00000 00196 //serial_print_str(" r2en="); 00197 //serial_print_int_hex_16bit(r2); 00198 00199 // Wait STC flag (Seek/Tune Complete, in “Status” register) 00200 // Not done yet! not sure which register it is... 00201 // Clear hmute Bit 00202 clear_bit(r1, R1_HARD_MUTE_ENABLE); 00203 i2c_write_eeprom_16bit(AR1000_DEV_ADDR, 1, r1); 00204 // register_values[02] = 0xB480; //set tune to 900kHz 00205 // register_values[03] = 0xA001; //turn off seek, seek up, set threshold to 1 00206 00207 // ar1000calibration(register_values); 00208 00209 // register_values[03] = 0xE001; //turns on seek 00210 00211 // ar1000calibration(register_values); 00212 00213 00214 00215 00216 }
void ar1000_write_register | ( | uns8 | reg, | |
uns16 | data | |||
) |
00077 { 00078 00079 i2c_write_eeprom_16bit(AR1000_DEV_ADDR, reg, data); 00080 00081 }
void ar1000_write_registers | ( | ) |
00060 { 00061 uns8 count; 00062 00063 }