Functions | |
void | ccld_enable_display (uns8 on) |
Enable display on ccld. | |
void | ccld_latch_data () |
void | ccld_setup_io () |
Setup IO to communicate with ccld chip. | |
void | ccld_tlc_normal_mode (void) |
void | ccld_tlc_special_mode (void) |
void | ccld_write_data (uns16 d) |
Send 16 bits to ccld. | |
void | ccld_write_data_byte (uns8 d) |
Send 8 bits of data to ccld chip. |
void ccld_enable_display | ( | uns8 | on | ) |
void ccld_latch_data | ( | void | ) |
void ccld_setup_io | ( | ) |
Setup IO to communicate with ccld chips
00057 { 00058 00059 clear_pin(ccld_clk_port, ccld_clk_pin); 00060 clear_pin(ccld_lat_port, ccld_lat_pin); 00061 #ifdef ccld_blk_port 00062 set_pin(ccld_blk_port, ccld_blk_pin); 00063 #endif 00064 make_output(ccld_sin_port, ccld_sin_pin); 00065 make_output(ccld_clk_port, ccld_clk_pin); 00066 #ifdef ccld_blk_port 00067 make_output(ccld_blk_port, ccld_blk_pin); 00068 #endif 00069 make_output(ccld_lat_port, ccld_lat_pin); 00070 00071 }
void ccld_tlc_normal_mode | ( | void | ) |
00159 { 00160 #ifdef ccld_blk_port 00161 set_pin(ccld_blk_port, ccld_blk_pin); 00162 #endif 00163 // pulse clk 00164 set_pin(ccld_clk_port, ccld_clk_pin); 00165 clear_pin(ccld_clk_port, ccld_clk_pin); 00166 00167 // set OE low 00168 #ifdef ccld_blk_port 00169 clear_pin(ccld_blk_port, ccld_blk_pin); 00170 #endif 00171 // pulse clk 00172 set_pin(ccld_clk_port, ccld_clk_pin); 00173 clear_pin(ccld_clk_port, ccld_clk_pin); 00174 00175 // set OE high 00176 #ifdef ccld_blk_port 00177 set_pin(ccld_blk_port, ccld_blk_pin); 00178 #endif 00179 00180 // pulse clk 00181 set_pin(ccld_clk_port, ccld_clk_pin); 00182 clear_pin(ccld_clk_port, ccld_clk_pin); 00183 00184 // pulse clk 00185 set_pin(ccld_clk_port, ccld_clk_pin); 00186 clear_pin(ccld_clk_port, ccld_clk_pin); 00187 00188 // pulse clk 00189 set_pin(ccld_clk_port, ccld_clk_pin); 00190 clear_pin(ccld_clk_port, ccld_clk_pin); 00191 00192 00193 }
void ccld_tlc_special_mode | ( | void | ) |
00118 { 00119 00120 #ifdef ccld_blk_port 00121 set_pin(ccld_blk_port, ccld_blk_pin); 00122 #endif 00123 // pulse clk 00124 set_pin(ccld_clk_port, ccld_clk_pin); 00125 clear_pin(ccld_clk_port, ccld_clk_pin); 00126 00127 // set OE low 00128 #ifdef ccld_blk_port 00129 clear_pin(ccld_blk_port, ccld_blk_pin); 00130 #endif 00131 // pulse clk 00132 set_pin(ccld_clk_port, ccld_clk_pin); 00133 clear_pin(ccld_clk_port, ccld_clk_pin); 00134 00135 // set OE high 00136 #ifdef ccld_blk_port 00137 set_pin(ccld_blk_port, ccld_blk_pin); 00138 #endif 00139 // pulse clk 00140 set_pin(ccld_clk_port, ccld_clk_pin); 00141 clear_pin(ccld_clk_port, ccld_clk_pin); 00142 00143 // now set latch high 00144 set_pin(ccld_lat_port, ccld_lat_pin); 00145 00146 // pulse clk 00147 set_pin(ccld_clk_port, ccld_clk_pin); 00148 clear_pin(ccld_clk_port, ccld_clk_pin); 00149 00150 // latch low 00151 clear_pin(ccld_lat_port, ccld_lat_pin); 00152 00153 // pulse clk 00154 set_pin(ccld_clk_port, ccld_clk_pin); 00155 clear_pin(ccld_clk_port, ccld_clk_pin); 00156 }
void ccld_write_data | ( | uns16 | d | ) |
Send d to ccld
00074 { 00075 00076 ccld_write_data_byte(d >> 8); 00077 ccld_write_data_byte(d & 0xff); 00078 00079 }
void ccld_write_data_byte | ( | uns8 | d | ) |
Send d1 to ccld chip
00082 { 00083 00084 uns8 count; 00085 00086 for (count=0; count<8; count++) { 00087 00088 // set data 00089 change_pin_var(ccld_sin_port, ccld_sin_pin, d.7); 00090 00091 // pulse clk 00092 00093 set_pin(ccld_clk_port, ccld_clk_pin); 00094 d <<= 1; 00095 00096 00097 clear_pin(ccld_clk_port, ccld_clk_pin); 00098 00099 } 00100 delay_us(100); 00101 }