FIR Filter Sample Project for Generic VHDL platform
Summary

12-tap FIR filter example.

Description

This example demonstrates the use of the UNROLL, PIPELINE and StageDelay pragmas to influence size and speed. By modifying the value of StageDelay you will obtain different maximum clock rates when synthesizing the generated HDL. By removing or commenting out the UNROLL pragmas, you will obtain larger cycle counts and correspondingly lower logic requirements.
 

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