EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# NAME DIR [LSB:MSB] SIG ATTRIBUTES 0A fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I_pin I 1 fpga_0_DDR2_SDRAM_DDR2_DQS_Div_I 1A fpga_0_DDR2_SDRAM_DDR2_DQ IO 31:0 fpga_0_DDR2_SDRAM_DDR2_DQ 2A fpga_0_DDR2_SDRAM_DDR2_DQS IO 3:0 fpga_0_DDR2_SDRAM_DDR2_DQS 3A fpga_0_DDR2_SDRAM_DDR2_DQS_n IO 3:0 fpga_0_DDR2_SDRAM_DDR2_DQS_n 4A fpga_0_DDR2_SDRAM_DDR2_Addr_pin O 12:0 fpga_0_DDR2_SDRAM_DDR2_Addr 5A fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin O 1:0 fpga_0_DDR2_SDRAM_DDR2_BankAddr 6A fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_CAS_n 7A fpga_0_DDR2_SDRAM_DDR2_CE_pin O 1 fpga_0_DDR2_SDRAM_DDR2_CE 8A fpga_0_DDR2_SDRAM_DDR2_CS_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_CS_n 9A fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin O 1:0 fpga_0_DDR2_SDRAM_DDR2_Clk_n 10A fpga_0_DDR2_SDRAM_DDR2_Clk_pin O 1:0 fpga_0_DDR2_SDRAM_DDR2_Clk 11A fpga_0_DDR2_SDRAM_DDR2_DM_pin O 3:0 fpga_0_DDR2_SDRAM_DDR2_DM 12A fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O_pin O 1 fpga_0_DDR2_SDRAM_DDR2_DQS_Div_O 13A fpga_0_DDR2_SDRAM_DDR2_ODT_pin O 1 fpga_0_DDR2_SDRAM_DDR2_ODT 14A fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_RAS_n				# NAME DIR [LSB:MSB] SIG ATTRIBUTES 15A fpga_0_DDR2_SDRAM_DDR2_WE_n_pin O 1 fpga_0_DDR2_SDRAM_DDR2_WE_n 16B fpga_0_Ethernet_MAC_PHY_col_pin I 1 fpga_0_Ethernet_MAC_PHY_col 17B fpga_0_Ethernet_MAC_PHY_crs_pin I 1 fpga_0_Ethernet_MAC_PHY_crs 18B fpga_0_Ethernet_MAC_PHY_dv_pin I 1 fpga_0_Ethernet_MAC_PHY_dv 19B fpga_0_Ethernet_MAC_PHY_rx_clk_pin I 1 fpga_0_Ethernet_MAC_PHY_rx_clk 20B fpga_0_Ethernet_MAC_PHY_rx_data_pin I 3:0 fpga_0_Ethernet_MAC_PHY_rx_data 21B fpga_0_Ethernet_MAC_PHY_rx_er_pin I 1 fpga_0_Ethernet_MAC_PHY_rx_er 22B fpga_0_Ethernet_MAC_PHY_tx_clk_pin I 1 fpga_0_Ethernet_MAC_PHY_tx_clk 23B fpga_0_Ethernet_MAC_PHY_rst_n_pin O 1 fpga_0_Ethernet_MAC_PHY_rst_n 24B fpga_0_Ethernet_MAC_PHY_tx_data_pin O 3:0 fpga_0_Ethernet_MAC_PHY_tx_data 25B fpga_0_Ethernet_MAC_PHY_tx_en_pin O 1 fpga_0_Ethernet_MAC_PHY_tx_en 26C fpga_0_RS232_Uart_1_RX_pin I 1 fpga_0_RS232_Uart_1_RX 27C fpga_0_RS232_Uart_1_TX_pin O 1 fpga_0_RS232_Uart_1_TX 28D sys_clk_pin I 1 dcm_clk_s  CLK  29E sys_rst_pin I 1 sys_rst_s  RESET