EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# NAME DIR [LSB:MSB] SIG ATTRIBUTES fpga_0_RS232_Uart_1_sin_pin I 1 fpga_0_RS232_Uart_1_sin fpga_0_RS232_Uart_1_sout_pin O 1 fpga_0_RS232_Uart_1_sout fpga_0_LEDs_8Bit_GPIO_IO_pin IO 0:7 fpga_0_LEDs_8Bit_GPIO_IO fpga_0_DDR2_SDRAM_32Mx64_DDR_ODT_pin O 1:0 fpga_0_DDR2_SDRAM_32Mx64_DDR_ODT fpga_0_DDR2_SDRAM_32Mx64_DDR_Addr_pin O 12:0 fpga_0_DDR2_SDRAM_32Mx64_DDR_Addr fpga_0_DDR2_SDRAM_32Mx64_DDR_BankAddr_pin O 1:0 fpga_0_DDR2_SDRAM_32Mx64_DDR_BankAddr fpga_0_DDR2_SDRAM_32Mx64_DDR_CASn_pin O 1 fpga_0_DDR2_SDRAM_32Mx64_DDR_CASn fpga_0_DDR2_SDRAM_32Mx64_DDR_CKE_pin O 1 fpga_0_DDR2_SDRAM_32Mx64_DDR_CKE fpga_0_DDR2_SDRAM_32Mx64_DDR_CSn_pin O 1 fpga_0_DDR2_SDRAM_32Mx64_DDR_CSn fpga_0_DDR2_SDRAM_32Mx64_DDR_RASn_pin O 1 fpga_0_DDR2_SDRAM_32Mx64_DDR_RASn fpga_0_DDR2_SDRAM_32Mx64_DDR_WEn_pin O 1 fpga_0_DDR2_SDRAM_32Mx64_DDR_WEn fpga_0_DDR2_SDRAM_32Mx64_DDR_DM_pin O 7:0 fpga_0_DDR2_SDRAM_32Mx64_DDR_DM DDR2_DQS IO 7:0 DDR2_DQS DDR2_DQS_N IO 7:0 DDR2_DQS_N DDR2_DQ IO 63:0 DDR2_DQ				# NAME DIR [LSB:MSB] SIG ATTRIBUTES fpga_0_DDR2_SDRAM_32Mx64_DDR_Clk_pin O 1:0 fpga_0_DDR2_SDRAM_32Mx64_DDR_Clk fpga_0_DDR2_SDRAM_32Mx64_DDR_Clkn_pin O 1:0 fpga_0_DDR2_SDRAM_32Mx64_DDR_Clkn phy_mii_int_n O 1 net_vcc sys_clk_pin I 1 dcm_clk_s  CLK  sys_rst_pin I 1 sys_rst_s  RESET  ppc440_mc_ddr2_0_mc_miaddrreadytoaccept_pin O 1 ppc440_mc_ddr2_0_mc_miaddrreadytoaccept plbv46_dvi_cntlr_0_TFT_LCD_VSYNC_pin O 1 plbv46_dvi_cntlr_0_TFT_LCD_VSYNC plbv46_dvi_cntlr_0_TFT_LCD_HSYNC_pin O 1 plbv46_dvi_cntlr_0_TFT_LCD_HSYNC plbv46_dvi_cntlr_0_TFT_LCD_DATA_pin O 11:0 plbv46_dvi_cntlr_0_TFT_LCD_DATA plbv46_dvi_cntlr_0_TFT_LCD_DE_pin O 1 plbv46_dvi_cntlr_0_TFT_LCD_DE plbv46_dvi_cntlr_0_TFT_LCD_CLK_N_pin O 1 plbv46_dvi_cntlr_0_TFT_LCD_CLK_N plbv46_dvi_cntlr_0_TFT_LCD_CLK_P_pin O 1 plbv46_dvi_cntlr_0_TFT_LCD_CLK_P xps_iic_0_Scl IO 1 xps_iic_0_Scl xps_iic_0_Sda IO 1 xps_iic_0_Sda vga_reset_pin O 1 sys_rst_s  RESET