main Project Status (10/03/2016 - 18:34:33)
Project File: RHD2000InterfaceXEM6310.xise Parser Errors: No Errors
Module Name: main Implementation State: Programming File Generated
Target Device: xc6slx45-2fgg484
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
412 Warnings (11 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
X 2 Failing Constraints
Environment: System Settings
  • Final Timing Score:
291137  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 6,320 54,576 11%  
    Number used as Flip Flops 6,320      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 11,212 27,288 41%  
    Number used as logic 10,998 27,288 40%  
        Number using O6 output only 9,734      
        Number using O5 output only 166      
        Number using O5 and O6 1,098      
        Number used as ROM 0      
    Number used as Memory 48 6,408 1%  
        Number used as Dual Port RAM 20      
            Number using O6 output only 12      
            Number using O5 output only 0      
            Number using O5 and O6 8      
        Number used as Single Port RAM 24      
            Number using O6 output only 16      
            Number using O5 output only 0      
            Number using O5 and O6 8      
        Number used as Shift Register 4      
            Number using O6 output only 4      
            Number using O5 output only 0      
            Number using O5 and O6 0      
    Number used exclusively as route-thrus 166      
        Number with same-slice register load 103      
        Number with same-slice carry load 63      
        Number with other load 0      
Number of occupied Slices 3,906 6,822 57%  
Number of MUXCYs used 1,684 13,644 12%  
Number of LUT Flip Flop pairs used 12,728      
    Number with an unused Flip Flop 6,732 12,728 52%  
    Number with an unused LUT 1,516 12,728 11%  
    Number of fully used LUT-FF pairs 4,480 12,728 35%  
    Number of unique control sets 193      
    Number of slice register sites lost
        to control set restrictions
592 54,576 1%  
Number of bonded IOBs 213 316 67%  
    Number of LOCed IOBs 213 213 100%  
    IOB Flip Flops 118      
    IOB Master Pads 1      
    IOB Slave Pads 1      
Number of RAMB16BWERs 58 116 50%  
Number of RAMB8BWERs 0 232 0%  
Number of BUFIO2/BUFIO2_2CLKs 2 32 6%  
    Number used as BUFIO2s 2      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 1 32 3%  
    Number used as BUFIO2FBs 1      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 6 16 37%  
    Number used as BUFGs 6      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 2 8 25%  
    Number used as DCMs 1      
    Number used as DCM_CLKGENs 1      
Number of ILOGIC2/ISERDES2s 36 376 9%  
    Number used as ILOGIC2s 36      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 37 376 9%  
    Number used as IODELAY2s 13      
    Number used as IODRP2s 2      
    Number used as IODRP2_MCBs 22      
Number of OLOGIC2/OSERDES2s 95 376 25%  
    Number used as OLOGIC2s 50      
    Number used as OSERDES2s 45      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 256 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 1 4 25%  
Number of DSP48A1s 8 58 13%  
Number of ICAPs 0 1 0%  
Number of MCBs 1 2 50%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 4 25%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 4.35      
 
Performance Summary [-]
Final Timing Score: 291137 (Setup: 260631, Hold: 30506, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: X 2 Failing Constraints    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSat Oct 15 17:14:57 20160321 Warnings (8 new)170 Infos (41 new)
Translation ReportCurrentSat Oct 15 17:15:09 201607 Warnings (3 new)12 Infos (0 new)
Map ReportCurrentSat Oct 15 17:18:36 2016042 Warnings (0 new)9 Infos (0 new)
Place and Route ReportCurrentSat Oct 15 18:34:10 201607 Warnings (0 new)1 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentSat Oct 15 18:34:26 201601 Warning (0 new)4 Infos (0 new)
Bitgen ReportCurrentSat Oct 15 18:35:10 2016034 Warnings (0 new)0
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentSat Oct 15 18:35:11 2016
WebTalk Log FileCurrentSat Oct 15 18:35:15 2016

Date Generated: 10/19/2016 - 18:07:01