ramtest Project Status (10/13/2012 - 11:37:10)
Project File: RHD2000InterfaceXEM6010.xise Parser Errors: No Errors
Module Name: ramtest Implementation State: Synthesized (Failed)
Target Device: xc6slx45-2fgg484
  • Errors:
 
Product Version:ISE 14.2
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateSat Oct 13 11:31:13 2012
WebTalk Log FileOut of DateSat Oct 13 11:31:18 2012

Date Generated: 10/13/2012 - 11:37:10