74 #elif !USE_CLOCK_TIMEOUT
76 void checkClockTimeout(
void) {
85 # define CLOCKTIMEOUT_MAX 200000L
86 # if ( defined(__PIC24H__) || defined(__dsPIC33F__) )
87 # define FRC_FCY 40000000L
88 # elif ( defined(__PIC24F__) || defined(__PIC24FK__) )
89 # define FRC_FCY 16000000L
90 # elif ( defined(__PIC24E__) || defined(__dsPIC33E__) )
91 # define FRC_FCY 60000000L
93 # error "Unknown processor."
98 static void configFrcUART(
void) {
100 # if ( defined(__PIC24H__) || defined(__dsPIC33F__) )
101 configClockFRCPLL_FCY40MHz();
102 # elif ( defined(__PIC24E__) || defined(__dsPIC33E__) )
103 configClockFRCPLL_FCY60MHz();
104 # elif ( defined(__PIC24F__) || defined(__PIC24FK__) )
106 configClockFRCPLL_FCY16MHz();
108 # error "Unknown processor."
115 # if (DEFAULT_UART == 1)
117 U1MODEbits.BRGH = FRC_BRGH;
118 # elif (DEFAULT_UART == 2)
120 U2MODEbits.BRGH = FRC_BRGH;
121 # elif (DEFAULT_UART == 3)
123 U3MODEbits.BRGH = FRC_BRGH;
124 # elif (DEFAULT_UART == 4)
126 U4MODEbits.BRGH = FRC_BRGH;
128 # error "Invalid DEFAULT_UART."
132 static uint32_t u32_timeoutCount;
133 static void checkClockTimeout(
void) {
138 if (u32_timeoutCount == 0xFFFFFFFF)
return;
143 if (u32_timeoutCount < CLOCKTIMEOUT_MAX)
return;
146 outString(
"\n\nYour clock choice failed to initialize. See " __FILE__
" line " TOSTRING(__LINE__)
" for more details.");
167 OSCCONBITS OSCCONBITS_copy;
180 OSCCONBITS_copy = OSCCONbits;
181 OSCCONBITS_copy.NOSC = u8_source;
182 OSCCONBITS_copy.OSWEN = 1;
184 __builtin_write_OSCCONH(
BITS2BYTEH(OSCCONBITS_copy));
186 __builtin_write_OSCCONL(
BITS2BYTEL(OSCCONBITS_copy));
194 # if USE_CLOCK_TIMEOUT
195 u32_timeoutCount = 0;
197 while (_OSWEN == 1) {
211 while (_COSC != u8_source) checkClockTimeout();
215 #if IS_CLOCK_CONFIG(SIM_CLOCK)
216 # warning "Clock configured for simulation, FCY = 1 Mhz."
218 #if GET_IS_SUPPORTED(SIM_CLOCK)
219 void configClockSim(
void) { }
223 #if IS_CLOCK_CONFIG(FRCPLL_FCY16MHz)
224 # warning "Clock configured for FRCPLL, FCY = 16 MHz."
226 #if GET_IS_SUPPORTED(FRCPLL_FCY16MHz)
227 void configClockFRCPLL_FCY16MHz(
void) {
251 # elif defined(PLLDIV_NODIV)
252 # warning "Ensure that the PLLDIV value is set to divide by 2 in the configuration bits for FRCPLL_FCY16MHz clock option!!"
256 # warning "PLL Enabled."
263 #if IS_CLOCK_CONFIG(FRC_FCY4MHz)
264 # warning "Clock configured for FRC, FCY = 4 MHz."
265 # warning "Baud rates of 19200 or lower recommended for this clock choice."
267 #if GET_IS_SUPPORTED(FRC_FCY4MHz)
268 void configClockFRC_FCY4MHz(
void) {
276 #if IS_CLOCK_CONFIG(PRI_NO_PLL_7372KHzCrystal)
277 # warning "Clock configured for a 7.372 MHz crystal primary oscillator, no PLL."
279 #if GET_IS_SUPPORTED(PRI_NO_PLL_7372KHzCrystal)
280 void configClockPRI_NO_PLL_7372KHzCrystal(
void) {
286 #if IS_CLOCK_CONFIG(FRC_FCY3685KHz)
287 # warning "Clock configured for FRC, FCY = 3.685 MHz."
289 #if GET_IS_SUPPORTED(FRC_FCY3685KHz)
290 void configClockFRC_FCY3685KHz(
void) {
301 #if IS_CLOCK_CONFIG(FRCPLL_FCY40MHz)
302 # warning "Clock configured for FRCPLL, FCY = 40 MHz."
304 #if GET_IS_SUPPORTED(FRCPLL_FCY40MHz)
305 void configClockFRCPLL_FCY40MHz(
void) {
333 #if IS_CLOCK_CONFIG(FRCPLL_FCY60MHz)
334 # warning "Clock configured for FRCPLL, FCY = 60 MHz."
336 #if GET_IS_SUPPORTED(FRCPLL_FCY60MHz)
337 void configClockFRCPLL_FCY60MHz(
void) {
361 #if IS_CLOCK_CONFIG(FRCPLL_FCY70MHz)
362 # warning "Clock configured for FRCPLL, FCY = 70 MHz."
364 #if GET_IS_SUPPORTED(FRCPLL_FCY70MHz)
365 void configClockFRCPLL_FCY70MHz(
void) {
391 #if IS_CLOCK_CONFIG(PRIPLL_7372KHzCrystal_40MHzFCY)
392 # warning "Clock configured for PRIPLL using a 7.3727 Mhz primary oscillator, FCY = 40 MHz."
394 #if GET_IS_SUPPORTED(PRIPLL_7372KHzCrystal_40MHzFCY)
395 void configClockPRIPLL_7372KHzCrystal_40MHzFCY(
void) {
408 #if IS_CLOCK_CONFIG(PRIPLL_8MHzCrystal_40MHzFCY)
409 # warning "Clock configured for PRIPLL using an 8.0 Mhz primary oscillator, FCY = 40 MHz."
411 #if GET_IS_SUPPORTED(PRIPLL_8MHzCrystal_40MHzFCY)
412 void configClockPRIPLL_8MHzCrystal_40MHzFCY(
void) {
429 #if IS_CLOCK_CONFIG(PRIPLL_8MHzCrystal_16MHzFCY)
430 # warning "Clock configured for PRIPLL using a 8.0 Mhz primary oscillator, FCY = 16 MHz."
432 #if GET_IS_SUPPORTED(PRIPLL_8MHzCrystal_16MHzFCY)
433 void configClockPRIPLL_8MHzCrystal_16MHzFCY(
void) {
457 # elif defined(PLLDIV_NODIV)
458 # warning "Ensure that the PLLDIV value is set to divide by 2 in the configuration bits for PRIPLL_8MHzCrystal_16MHzFCY clock option!!"
462 # warning "PLL Enabled."
469 #if IS_CLOCK_CONFIG(PRI_8MHzCrystal_4MHzFCY)
470 # warning "Clock configured for PRI using a 8.0 Mhz primary oscillator, FCY = 4 MHz."
471 # warning "Baud rates of 19200 or lower recommended for this clock choice."
473 #if GET_IS_SUPPORTED(PRI_8MHzCrystal_4MHzFCY)
474 void configClockPRI_8MHzCrystal_4MHzFCY(
void) {