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pic24_ecan.h
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1 /*
2  * "Copyright (c) 2008 Robert B. Reese, Bryan A. Jones, J. W. Bruce ("AUTHORS")"
3  * All rights reserved.
4  * (R. Reese, reese_AT_ece.msstate.edu, Mississippi State University)
5  * (B. A. Jones, bjones_AT_ece.msstate.edu, Mississippi State University)
6  * (J. W. Bruce, jwbruce_AT_ece.msstate.edu, Mississippi State University)
7  *
8  * Permission to use, copy, modify, and distribute this software and its
9  * documentation for any purpose, without fee, and without written agreement is
10  * hereby granted, provided that the above copyright notice, the following
11  * two paragraphs and the authors appear in all copies of this software.
12  *
13  * IN NO EVENT SHALL THE "AUTHORS" BE LIABLE TO ANY PARTY FOR
14  * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
15  * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE "AUTHORS"
16  * HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17  *
18  * THE "AUTHORS" SPECIFICALLY DISCLAIMS ANY WARRANTIES,
19  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
20  * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
21  * ON AN "AS IS" BASIS, AND THE "AUTHORS" HAS NO OBLIGATION TO
22  * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
23  *
24  * Please maintain this header in its entirety when copying/modifying
25  * these files.
26  *
27  *
28  */
29 
30 #pragma once
31 
32 #include <stdint.h>
33 #include "pic24_unions.h"
34 #include "pic24_chip.h"
35 #include "pic24_clockfreq.h"
36 
37 // Only include if this ECAN Module exists.
38 #if (NUM_ECAN_MODS >= 1)
39 
40 // Documentation for this file. If the \file tag isn't present,
41 // this file won't be documented.
42 // Note: place this comment below the #if NUM_ECAN_MODS so Doxygen
43 // will only see it once.
44 /** \file
45 * ECAN Header File
46 */
47 
48 #ifndef ECAN_1TIME_HEADER_DEFS
49 
50 #define ECAN_MODE_NORMAL 0
51 #define ECAN_MODE_DISABLED 1
52 #define ECAN_MODE_LOOPBACK 2
53 #define ECAN_MODE_LISTEN_ONLY 3
54 #define ECAN_MODE_CONFIGURE 4
55 #define ECAN_LISTEN_ALL_MESSAGES 7
56 
57 // CANCKS in CiCTRL1 ECAN Register
58 // CANCKS: ECANx Module Clock (FCAN) Source Select Bit
59 //
60 // The CANCKS bit was defined in the CiCTRL1 register when the initial PIC24
61 // library and text was written (2008). The following definitions were used
62 // for the CANCKS bit. In May 2009, datasheet revision history says
63 // Changed bit 11 in the ECAN Control Register 1 (CiCTRL1) to Reserved
64 // (see Register 19-1).
65 // Thus, these definitions are no longer needed in the non-E families of the
66 // PIC24/dsPIC [JWB May 2014]
67 //#define ECAN_FCAN_IS_FCY 1
68 //#define ECAN_FCAN_IS_OSC 0
69 
70 // The CANCKS bit was returned to the "E" family in the same register
71 // (CiCTRL1) and bit location (bit 11). See the revision history entry in
72 // the ECAN chapter of the E-family FRM for March 2011. However, the
73 // meaning of the CANCKS bit is now completely different than original
74 // CANCKS bit used in 2008-2009 [JWB May 2014]
75 #ifdef __dsPIC33E__
76 # define ECAN_FCAN_IS_2FP 1 // FCAN is equal to 2 * FP
77 # define ECAN_FCAN_IS_FP 0 // FCAN is equal to FP
78 #endif
79 
80 //CiCFG2 register (Baud rate config 2 register)
81 #define ECAN_NO_WAKEUP 0x4000
82 #define ECAN_SEG2PH_8TQ (0x0007 << 8)
83 #define ECAN_SEG2PH_7TQ (0x0006 << 8)
84 #define ECAN_SEG2PH_6TQ (0x0005 << 8)
85 #define ECAN_SEG2PH_5TQ (0x0004 << 8)
86 #define ECAN_SEG2PH_4TQ (0x0003 << 8)
87 #define ECAN_SEG2PH_3TQ (0x0002 << 8)
88 #define ECAN_SEG2PH_2TQ (0x0001 << 8)
89 #define ECAN_SEG2PH_1TQ (0x0000 << 8)
90 
91 #define ECAN_SEG2_PROGRAMMABLE 0x0080
92 #define ECAN_SEG2_FIXED 0x0000
93 
94 #define ECAN_SAMPLE_3TIMES 0x0040
95 #define ECAN_SAMPLE_1TIMES 0x0000
96 
97 #define ECAN_SEG1PH_8TQ (0x0007 << 3)
98 #define ECAN_SEG1PH_7TQ (0x0006 << 3)
99 #define ECAN_SEG1PH_6TQ (0x0005 << 3)
100 #define ECAN_SEG1PH_5TQ (0x0004 << 3)
101 #define ECAN_SEG1PH_4TQ (0x0003 << 3)
102 #define ECAN_SEG1PH_3TQ (0x0002 << 3)
103 #define ECAN_SEG1PH_2TQ (0x0001 << 3)
104 #define ECAN_SEG1PH_1TQ (0x0000 << 3)
105 
106 #define ECAN_PRSEG_8TQ 0x0007
107 #define ECAN_PRSEG_7TQ 0x0006
108 #define ECAN_PRSEG_6TQ 0x0005
109 #define ECAN_PRSEG_5TQ 0x0004
110 #define ECAN_PRSEG_4TQ 0x0003
111 #define ECAN_PRSEG_3TQ 0x0002
112 #define ECAN_PRSEG_2TQ 0x0001
113 #define ECAN_PRSEG_1TQ 0x0000
114 
115 //CiCFG1 register (Baud rate config 1 register)
116 #define ECAN_SYNC_JUMP_4 (0x0003 << 6)
117 #define ECAN_SYNC_JUMP_3 (0x0002 << 6)
118 #define ECAN_SYNC_JUMP_2 (0x0001 << 6)
119 #define ECAN_SYNC_JUMP_1 (0x0000 << 6)
120 
121 #define ECAN_PRE_2x64 0x003f
122 #define ECAN_PRE_2x63 0x003e
123 #define ECAN_PRE_2x62 0x003d
124 #define ECAN_PRE_2x61 0x003c
125 #define ECAN_PRE_2x60 0x003b
126 #define ECAN_PRE_2x59 0x003a
127 #define ECAN_PRE_2x58 0x0039
128 #define ECAN_PRE_2x57 0x0038
129 #define ECAN_PRE_2x56 0x0037
130 #define ECAN_PRE_2x55 0x0036
131 #define ECAN_PRE_2x54 0x0035
132 #define ECAN_PRE_2x53 0x0034
133 #define ECAN_PRE_2x52 0x0033
134 #define ECAN_PRE_2x51 0x0032
135 #define ECAN_PRE_2x50 0x0031
136 #define ECAN_PRE_2x49 0x0030
137 #define ECAN_PRE_2x48 0x002f
138 #define ECAN_PRE_2x47 0x002e
139 #define ECAN_PRE_2x46 0x002d
140 #define ECAN_PRE_2x45 0x002c
141 #define ECAN_PRE_2x44 0x002b
142 #define ECAN_PRE_2x43 0x002a
143 #define ECAN_PRE_2x42 0x0029
144 #define ECAN_PRE_2x41 0x0028
145 #define ECAN_PRE_2x40 0x0027
146 #define ECAN_PRE_2x39 0x0026
147 #define ECAN_PRE_2x38 0x0025
148 #define ECAN_PRE_2x37 0x0024
149 #define ECAN_PRE_2x36 0x0023
150 #define ECAN_PRE_2x35 0x0022
151 #define ECAN_PRE_2x34 0x0021
152 #define ECAN_PRE_2x33 0x0020
153 #define ECAN_PRE_2x32 0x001f
154 #define ECAN_PRE_2x31 0x001e
155 #define ECAN_PRE_2x30 0x001d
156 #define ECAN_PRE_2x29 0x001c
157 #define ECAN_PRE_2x28 0x001b
158 #define ECAN_PRE_2x27 0x001a
159 #define ECAN_PRE_2x26 0x0019
160 #define ECAN_PRE_2x25 0x0018
161 #define ECAN_PRE_2x24 0x0017
162 #define ECAN_PRE_2x23 0x0016
163 #define ECAN_PRE_2x22 0x0015
164 #define ECAN_PRE_2x21 0x0014
165 #define ECAN_PRE_2x20 0x0013
166 #define ECAN_PRE_2x19 0x0012
167 #define ECAN_PRE_2x18 0x0011
168 #define ECAN_PRE_2x17 0x0010
169 #define ECAN_PRE_2x16 0x000f
170 #define ECAN_PRE_2x15 0x000e
171 #define ECAN_PRE_2x14 0x000d
172 #define ECAN_PRE_2x13 0x000c
173 #define ECAN_PRE_2x12 0x000b
174 #define ECAN_PRE_2x11 0x000a
175 #define ECAN_PRE_2x10 0x0009
176 #define ECAN_PRE_2x9 0x0008
177 #define ECAN_PRE_2x8 0x0007
178 #define ECAN_PRE_2x7 0x0006
179 #define ECAN_PRE_2x6 0x0005
180 #define ECAN_PRE_2x5 0x0004
181 #define ECAN_PRE_2x4 0x0003
182 #define ECAN_PRE_2x3 0x0002
183 #define ECAN_PRE_2x2 0x0001
184 #define ECAN_PRE_2x1 0x0000
185 
186 //CiFCTRL register (FIFO Control register)
187 #define ECAN_DMA_BUF_SIZE_32 (0x0006 << 13)
188 #define ECAN_DMA_BUF_SIZE_24 (0x0005 << 13)
189 #define ECAN_DMA_BUF_SIZE_16 (0x0004 << 13)
190 #define ECAN_DMA_BUF_SIZE_12 (0x0003 << 13)
191 #define ECAN_DMA_BUF_SIZE_8 (0x0002 << 13)
192 #define ECAN_DMA_BUF_SIZE_6 (0x0001 << 13)
193 #define ECAN_DMA_BUF_SIZE_4 (0x0000 << 13)
194 
195 
196 #define ECAN_FIFO_START_AREA_31 31
197 #define ECAN_FIFO_START_AREA_30 30
198 #define ECAN_FIFO_START_AREA_29 29
199 #define ECAN_FIFO_START_AREA_28 28
200 #define ECAN_FIFO_START_AREA_27 27
201 #define ECAN_FIFO_START_AREA_26 26
202 #define ECAN_FIFO_START_AREA_25 25
203 #define ECAN_FIFO_START_AREA_24 24
204 #define ECAN_FIFO_START_AREA_23 23
205 #define ECAN_FIFO_START_AREA_22 22
206 #define ECAN_FIFO_START_AREA_21 21
207 #define ECAN_FIFO_START_AREA_20 20
208 #define ECAN_FIFO_START_AREA_19 19
209 #define ECAN_FIFO_START_AREA_18 18
210 #define ECAN_FIFO_START_AREA_17 17
211 #define ECAN_FIFO_START_AREA_16 16
212 #define ECAN_FIFO_START_AREA_15 15
213 #define ECAN_FIFO_START_AREA_14 14
214 #define ECAN_FIFO_START_AREA_13 13
215 #define ECAN_FIFO_START_AREA_12 12
216 #define ECAN_FIFO_START_AREA_11 11
217 #define ECAN_FIFO_START_AREA_10 10
218 #define ECAN_FIFO_START_AREA_9 9
219 #define ECAN_FIFO_START_AREA_8 8
220 #define ECAN_FIFO_START_AREA_7 7
221 #define ECAN_FIFO_START_AREA_6 6
222 #define ECAN_FIFO_START_AREA_5 5
223 #define ECAN_FIFO_START_AREA_4 4
224 #define ECAN_FIFO_START_AREA_3 3
225 #define ECAN_FIFO_START_AREA_2 2
226 #define ECAN_FIFO_START_AREA_1 1
227 #define ECAN_FIFO_START_AREA_0 0
228 
229 //CiRXFnSID register
230 #define ECAN_MATCH_EID 0x0008
231 #define ECAN_MATCH_SID 0x0000
232 
233 #define ECAN_USE_FIFO 0xF
234 
235 //CiTRmnCON TXRX buffer control
236 #define ECAN_RX_BUFF 0
237 #define ECAN_TX_BUFF 1
238 
239 
240 //Data structure for ECAN Data Frame
241 typedef struct _ECANW0 {
242  unsigned IDE: 1;
243  unsigned SRR:1;
244  unsigned SID:11;
245 } ECANW0;
246 typedef struct _ECANW1 {
247  unsigned EID17_6: 12;
248 } ECANW1;
249 
250 typedef struct _ECANW2 {
251  unsigned DLC:4;
252  unsigned RB0:1;
253  unsigned :3;
254  unsigned RB1:1;
255  unsigned RTR:1;
256  unsigned EID5_0:6;
257 } ECANW2;
258 
259 typedef struct _ECANW7 {
260  unsigned :8;
261  unsigned FILHIT:5;
262  unsigned :3;
263 } ECANW7;
264 
265 
266 
267 typedef struct _ECANMSG {
268  ECANW0 w0;
269  ECANW1 w1;
270  ECANW2 w2;
271  union64 data;
272  ECANW7 w7;
273 } ECANMSG;
274 
275 
276 void formatStandardDataFrameECAN (ECANMSG* p_ecanmsg, uint16_t u16_id, uint8_t u8_len);
277 void formatExtendedDataFrameECAN (ECANMSG* p_ecanmsg, uint32_t u32_id, uint8_t u8_len);
278 uint32_t getIdExtendedDataFrameECAN (ECANMSG* p_ecanmsg);
279 
280 #define ECAN_1TIME_HEADER_DEFS
281 #endif
282 
283 
284 
285 
286 #ifdef _C1IF
287 /** Waits until all characters placed in the UART have been sent. */
288 inline static void CHANGE_MODE_ECAN1(uint16_t u16_mode) {
289  C1CTRL1bits.REQOP = u16_mode;
290  while(C1CTRL1bits.OPMODE != u16_mode);
291 }
292 
293 /** Return the number (0-31) of the next ECAN FIFO read buffer
294  */
295 #define GET_FIFO_READBUFFER_ECAN1() (C1FIFO & 0x1F)
296 
297 void configBaudECAN1(void);
298 void clrRxFullFlagECAN1(uint8_t u8_bufNum);
300 void clrRxFullOvfFlagsECAN1(void);
301 void configTxRxBufferECAN1(uint8_t u8_bufNum, uint8_t u8_type, uint8_t u8_priority);
302 void configRxFilterECAN1(uint8_t u8_filtNum, uint32_t u32_id, uint8_t u8_idType, uint8_t u8_bufnum, uint8_t u8_maskReg);
303 void configRxMaskECAN1(uint8_t u8_maskNum, uint32_t u32_idMask, uint8_t u8_idType, uint8_t u8_matchType);
304 void startTxECAN1(uint8_t u8_bufNum);
306 
307 #endif
308 
309 
310 #endif // #if (NUM_ECAN_MODS >= 1)
311 
312 
313 
314 
315 
316 
317 
318 /*
319  * "Copyright (c) 2008 Robert B. Reese, Bryan A. Jones, J. W. Bruce ("AUTHORS")"
320  * All rights reserved.
321  * (R. Reese, reese_AT_ece.msstate.edu, Mississippi State University)
322  * (B. A. Jones, bjones_AT_ece.msstate.edu, Mississippi State University)
323  * (J. W. Bruce, jwbruce_AT_ece.msstate.edu, Mississippi State University)
324  *
325  * Permission to use, copy, modify, and distribute this software and its
326  * documentation for any purpose, without fee, and without written agreement is
327  * hereby granted, provided that the above copyright notice, the following
328  * two paragraphs and the authors appear in all copies of this software.
329  *
330  * IN NO EVENT SHALL THE "AUTHORS" BE LIABLE TO ANY PARTY FOR
331  * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
332  * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE "AUTHORS"
333  * HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
334  *
335  * THE "AUTHORS" SPECIFICALLY DISCLAIMS ANY WARRANTIES,
336  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
337  * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
338  * ON AN "AS IS" BASIS, AND THE "AUTHORS" HAS NO OBLIGATION TO
339  * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
340  *
341  * Please maintain this header in its entirety when copying/modifying
342  * these files.
343  *
344  *
345  */
346 
347 #pragma once
348 
349 #include <stdint.h>
350 #include "pic24_unions.h"
351 #include "pic24_chip.h"
352 #include "pic24_clockfreq.h"
353 
354 // Only include if this ECAN Module exists.
355 #if (NUM_ECAN_MODS >= 2)
356 
357 // Documentation for this file. If the \file tag isn't present,
358 // this file won't be documented.
359 // Note: place this comment below the #if NUM_ECAN_MODS so Doxygen
360 // will only see it once.
361 /** \file
362 * ECAN Header File
363 */
364 
365 #ifndef ECAN_1TIME_HEADER_DEFS
366 
367 #define ECAN_MODE_NORMAL 0
368 #define ECAN_MODE_DISABLED 1
369 #define ECAN_MODE_LOOPBACK 2
370 #define ECAN_MODE_LISTEN_ONLY 3
371 #define ECAN_MODE_CONFIGURE 4
372 #define ECAN_LISTEN_ALL_MESSAGES 7
373 
374 // CANCKS in CiCTRL1 ECAN Register
375 // CANCKS: ECANx Module Clock (FCAN) Source Select Bit
376 //
377 // The CANCKS bit was defined in the CiCTRL1 register when the initial PIC24
378 // library and text was written (2008). The following definitions were used
379 // for the CANCKS bit. In May 2009, datasheet revision history says
380 // Changed bit 11 in the ECAN Control Register 1 (CiCTRL1) to Reserved
381 // (see Register 19-1).
382 // Thus, these definitions are no longer needed in the non-E families of the
383 // PIC24/dsPIC [JWB May 2014]
384 //#define ECAN_FCAN_IS_FCY 1
385 //#define ECAN_FCAN_IS_OSC 0
386 
387 // The CANCKS bit was returned to the "E" family in the same register
388 // (CiCTRL1) and bit location (bit 11). See the revision history entry in
389 // the ECAN chapter of the E-family FRM for March 2011. However, the
390 // meaning of the CANCKS bit is now completely different than original
391 // CANCKS bit used in 2008-2009 [JWB May 2014]
392 #ifdef __dsPIC33E__
393 # define ECAN_FCAN_IS_2FP 1 // FCAN is equal to 2 * FP
394 # define ECAN_FCAN_IS_FP 0 // FCAN is equal to FP
395 #endif
396 
397 //CiCFG2 register (Baud rate config 2 register)
398 #define ECAN_NO_WAKEUP 0x4000
399 #define ECAN_SEG2PH_8TQ (0x0007 << 8)
400 #define ECAN_SEG2PH_7TQ (0x0006 << 8)
401 #define ECAN_SEG2PH_6TQ (0x0005 << 8)
402 #define ECAN_SEG2PH_5TQ (0x0004 << 8)
403 #define ECAN_SEG2PH_4TQ (0x0003 << 8)
404 #define ECAN_SEG2PH_3TQ (0x0002 << 8)
405 #define ECAN_SEG2PH_2TQ (0x0001 << 8)
406 #define ECAN_SEG2PH_1TQ (0x0000 << 8)
407 
408 #define ECAN_SEG2_PROGRAMMABLE 0x0080
409 #define ECAN_SEG2_FIXED 0x0000
410 
411 #define ECAN_SAMPLE_3TIMES 0x0040
412 #define ECAN_SAMPLE_1TIMES 0x0000
413 
414 #define ECAN_SEG1PH_8TQ (0x0007 << 3)
415 #define ECAN_SEG1PH_7TQ (0x0006 << 3)
416 #define ECAN_SEG1PH_6TQ (0x0005 << 3)
417 #define ECAN_SEG1PH_5TQ (0x0004 << 3)
418 #define ECAN_SEG1PH_4TQ (0x0003 << 3)
419 #define ECAN_SEG1PH_3TQ (0x0002 << 3)
420 #define ECAN_SEG1PH_2TQ (0x0001 << 3)
421 #define ECAN_SEG1PH_1TQ (0x0000 << 3)
422 
423 #define ECAN_PRSEG_8TQ 0x0007
424 #define ECAN_PRSEG_7TQ 0x0006
425 #define ECAN_PRSEG_6TQ 0x0005
426 #define ECAN_PRSEG_5TQ 0x0004
427 #define ECAN_PRSEG_4TQ 0x0003
428 #define ECAN_PRSEG_3TQ 0x0002
429 #define ECAN_PRSEG_2TQ 0x0001
430 #define ECAN_PRSEG_1TQ 0x0000
431 
432 //CiCFG1 register (Baud rate config 1 register)
433 #define ECAN_SYNC_JUMP_4 (0x0003 << 6)
434 #define ECAN_SYNC_JUMP_3 (0x0002 << 6)
435 #define ECAN_SYNC_JUMP_2 (0x0001 << 6)
436 #define ECAN_SYNC_JUMP_1 (0x0000 << 6)
437 
438 #define ECAN_PRE_2x64 0x003f
439 #define ECAN_PRE_2x63 0x003e
440 #define ECAN_PRE_2x62 0x003d
441 #define ECAN_PRE_2x61 0x003c
442 #define ECAN_PRE_2x60 0x003b
443 #define ECAN_PRE_2x59 0x003a
444 #define ECAN_PRE_2x58 0x0039
445 #define ECAN_PRE_2x57 0x0038
446 #define ECAN_PRE_2x56 0x0037
447 #define ECAN_PRE_2x55 0x0036
448 #define ECAN_PRE_2x54 0x0035
449 #define ECAN_PRE_2x53 0x0034
450 #define ECAN_PRE_2x52 0x0033
451 #define ECAN_PRE_2x51 0x0032
452 #define ECAN_PRE_2x50 0x0031
453 #define ECAN_PRE_2x49 0x0030
454 #define ECAN_PRE_2x48 0x002f
455 #define ECAN_PRE_2x47 0x002e
456 #define ECAN_PRE_2x46 0x002d
457 #define ECAN_PRE_2x45 0x002c
458 #define ECAN_PRE_2x44 0x002b
459 #define ECAN_PRE_2x43 0x002a
460 #define ECAN_PRE_2x42 0x0029
461 #define ECAN_PRE_2x41 0x0028
462 #define ECAN_PRE_2x40 0x0027
463 #define ECAN_PRE_2x39 0x0026
464 #define ECAN_PRE_2x38 0x0025
465 #define ECAN_PRE_2x37 0x0024
466 #define ECAN_PRE_2x36 0x0023
467 #define ECAN_PRE_2x35 0x0022
468 #define ECAN_PRE_2x34 0x0021
469 #define ECAN_PRE_2x33 0x0020
470 #define ECAN_PRE_2x32 0x001f
471 #define ECAN_PRE_2x31 0x001e
472 #define ECAN_PRE_2x30 0x001d
473 #define ECAN_PRE_2x29 0x001c
474 #define ECAN_PRE_2x28 0x001b
475 #define ECAN_PRE_2x27 0x001a
476 #define ECAN_PRE_2x26 0x0019
477 #define ECAN_PRE_2x25 0x0018
478 #define ECAN_PRE_2x24 0x0017
479 #define ECAN_PRE_2x23 0x0016
480 #define ECAN_PRE_2x22 0x0015
481 #define ECAN_PRE_2x21 0x0014
482 #define ECAN_PRE_2x20 0x0013
483 #define ECAN_PRE_2x19 0x0012
484 #define ECAN_PRE_2x18 0x0011
485 #define ECAN_PRE_2x17 0x0010
486 #define ECAN_PRE_2x16 0x000f
487 #define ECAN_PRE_2x15 0x000e
488 #define ECAN_PRE_2x14 0x000d
489 #define ECAN_PRE_2x13 0x000c
490 #define ECAN_PRE_2x12 0x000b
491 #define ECAN_PRE_2x11 0x000a
492 #define ECAN_PRE_2x10 0x0009
493 #define ECAN_PRE_2x9 0x0008
494 #define ECAN_PRE_2x8 0x0007
495 #define ECAN_PRE_2x7 0x0006
496 #define ECAN_PRE_2x6 0x0005
497 #define ECAN_PRE_2x5 0x0004
498 #define ECAN_PRE_2x4 0x0003
499 #define ECAN_PRE_2x3 0x0002
500 #define ECAN_PRE_2x2 0x0001
501 #define ECAN_PRE_2x1 0x0000
502 
503 //CiFCTRL register (FIFO Control register)
504 #define ECAN_DMA_BUF_SIZE_32 (0x0006 << 13)
505 #define ECAN_DMA_BUF_SIZE_24 (0x0005 << 13)
506 #define ECAN_DMA_BUF_SIZE_16 (0x0004 << 13)
507 #define ECAN_DMA_BUF_SIZE_12 (0x0003 << 13)
508 #define ECAN_DMA_BUF_SIZE_8 (0x0002 << 13)
509 #define ECAN_DMA_BUF_SIZE_6 (0x0001 << 13)
510 #define ECAN_DMA_BUF_SIZE_4 (0x0000 << 13)
511 
512 
513 #define ECAN_FIFO_START_AREA_31 31
514 #define ECAN_FIFO_START_AREA_30 30
515 #define ECAN_FIFO_START_AREA_29 29
516 #define ECAN_FIFO_START_AREA_28 28
517 #define ECAN_FIFO_START_AREA_27 27
518 #define ECAN_FIFO_START_AREA_26 26
519 #define ECAN_FIFO_START_AREA_25 25
520 #define ECAN_FIFO_START_AREA_24 24
521 #define ECAN_FIFO_START_AREA_23 23
522 #define ECAN_FIFO_START_AREA_22 22
523 #define ECAN_FIFO_START_AREA_21 21
524 #define ECAN_FIFO_START_AREA_20 20
525 #define ECAN_FIFO_START_AREA_19 19
526 #define ECAN_FIFO_START_AREA_18 18
527 #define ECAN_FIFO_START_AREA_17 17
528 #define ECAN_FIFO_START_AREA_16 16
529 #define ECAN_FIFO_START_AREA_15 15
530 #define ECAN_FIFO_START_AREA_14 14
531 #define ECAN_FIFO_START_AREA_13 13
532 #define ECAN_FIFO_START_AREA_12 12
533 #define ECAN_FIFO_START_AREA_11 11
534 #define ECAN_FIFO_START_AREA_10 10
535 #define ECAN_FIFO_START_AREA_9 9
536 #define ECAN_FIFO_START_AREA_8 8
537 #define ECAN_FIFO_START_AREA_7 7
538 #define ECAN_FIFO_START_AREA_6 6
539 #define ECAN_FIFO_START_AREA_5 5
540 #define ECAN_FIFO_START_AREA_4 4
541 #define ECAN_FIFO_START_AREA_3 3
542 #define ECAN_FIFO_START_AREA_2 2
543 #define ECAN_FIFO_START_AREA_1 1
544 #define ECAN_FIFO_START_AREA_0 0
545 
546 //CiRXFnSID register
547 #define ECAN_MATCH_EID 0x0008
548 #define ECAN_MATCH_SID 0x0000
549 
550 #define ECAN_USE_FIFO 0xF
551 
552 //CiTRmnCON TXRX buffer control
553 #define ECAN_RX_BUFF 0
554 #define ECAN_TX_BUFF 1
555 
556 
557 //Data structure for ECAN Data Frame
558 typedef struct _ECANW0 {
559  unsigned IDE: 1;
560  unsigned SRR:1;
561  unsigned SID:11;
562 } ECANW0;
563 typedef struct _ECANW1 {
564  unsigned EID17_6: 12;
565 } ECANW1;
566 
567 typedef struct _ECANW2 {
568  unsigned DLC:4;
569  unsigned RB0:1;
570  unsigned :3;
571  unsigned RB1:1;
572  unsigned RTR:1;
573  unsigned EID5_0:6;
574 } ECANW2;
575 
576 typedef struct _ECANW7 {
577  unsigned :8;
578  unsigned FILHIT:5;
579  unsigned :3;
580 } ECANW7;
581 
582 
583 
584 typedef struct _ECANMSG {
585  ECANW0 w0;
586  ECANW1 w1;
587  ECANW2 w2;
588  union64 data;
589  ECANW7 w7;
590 } ECANMSG;
591 
592 
593 void formatStandardDataFrameECAN (ECANMSG* p_ecanmsg, uint16_t u16_id, uint8_t u8_len);
594 void formatExtendedDataFrameECAN (ECANMSG* p_ecanmsg, uint32_t u32_id, uint8_t u8_len);
595 uint32_t getIdExtendedDataFrameECAN (ECANMSG* p_ecanmsg);
596 
597 #define ECAN_1TIME_HEADER_DEFS
598 #endif
599 
600 
601 
602 
603 #ifdef _C2IF
604 /** Waits until all characters placed in the UART have been sent. */
605 inline static void CHANGE_MODE_ECAN2(uint16_t u16_mode) {
606  C2CTRL1bits.REQOP = u16_mode;
607  while(C2CTRL1bits.OPMODE != u16_mode);
608 }
609 
610 /** Return the number (0-31) of the next ECAN FIFO read buffer
611  */
612 #define GET_FIFO_READBUFFER_ECAN2() (C2FIFO & 0x1F)
613 
614 void configBaudECAN2(void);
615 void clrRxFullFlagECAN2(uint8_t u8_bufNum);
616 uint8_t getRxFullFlagECAN2(uint8_t u8_bufNum);
617 void clrRxFullOvfFlagsECAN2(void);
618 void configTxRxBufferECAN2(uint8_t u8_bufNum, uint8_t u8_type, uint8_t u8_priority);
619 void configRxFilterECAN2(uint8_t u8_filtNum, uint32_t u32_id, uint8_t u8_idType, uint8_t u8_bufnum, uint8_t u8_maskReg);
620 void configRxMaskECAN2(uint8_t u8_maskNum, uint32_t u32_idMask, uint8_t u8_idType, uint8_t u8_matchType);
621 void startTxECAN2(uint8_t u8_bufNum);
622 uint8_t getTxInProgressECAN2(uint8_t u8_bufNum);
623 
624 #endif
625 
626 
627 #endif // #if (NUM_ECAN_MODS >= 2)
628 
629 
630 
631 
632 
633 
634