23 #define getTimerPrescale(TxCONbits) getTimerPrescaleBits(TxCONbits.TCKPS)
25 #define MS_TO_TICKS(ms, pre) ((FCY/1000L/(pre))*(ms))
28 uint16_t
msToU16Ticks(uint16_t u16_ms, uint16_t u16_pre);
29 uint16_t
usToU16Ticks(uint16_t u16_us, uint16_t u16_pre);
30 uint32_t
usToU32Ticks(uint32_t u32_us, uint16_t u16_pre);
31 uint32_t
ticksToMs (uint32_t u32_ticks, uint16_t u16_tmrPre);
32 uint32_t
ticksToUs (uint32_t u32_ticks, uint16_t u16_tmrPre);
33 uint32_t
ticksToNs (uint32_t u32_ticks, uint16_t u16_tmrPre);
36 uint32_t
computeDeltaTicksLong(uint16_t u16_start, uint16_t u16_end, uint16_t u16_tmrPR, uint16_t u16_oflows);
37 uint16_t
computeDeltaTicks(uint16_t u16_start, uint16_t u16_end, uint16_t u16_tmrPR);
53 #define T1_OFF_ON_MASK (~T1_ON)
55 #define T1_IDLE_STOP 0x2000
56 #define T1_IDLE_CON 0x0000
57 #define T1_IDLE_MASK (~T1_IDLE_STOP)
59 #define T1_GATE_ON 0x0040
60 #define T1_GATE_OFF 0x0000
61 #define T1_GATE_MASK (~T1_GATE_ON)
63 #define T1_PS_1_1 0x0000
64 #define T1_PS_1_8 0x0010
65 #define T1_PS_1_64 0x0020
66 #define T1_PS_1_256 0x0030
67 #define T1_PS_MASK (~T1_PS_1_256)
69 #define T1_SYNC_EXT_ON 0x0004
70 #define T1_SYNC_EXT_OFF 0x0000
71 #define T1_SYNC_EXT_MASK (~T1_SYNC_EXT_ON)
73 #define T1_SOURCE_EXT 0x0002
74 #define T1_SOURCE_INT 0x0000
75 #define T1_SOURCE_MASK (~T1_SOURCE_EXT)
81 #define T2_OFF_ON_MASK (~T2_ON)
83 #define T2_IDLE_STOP 0x2000
84 #define T2_IDLE_CON 0x0000
85 #define T2_IDLE_MASK (~T2_IDLE_STOP)
87 #define T2_GATE_ON 0x0040
88 #define T2_GATE_OFF 0x0000
89 #define T2_GATE_MASK (~T2_GATE_ON)
91 #define T2_PS_1_1 0x0000
92 #define T2_PS_1_8 0x0010
93 #define T2_PS_1_64 0x0020
94 #define T2_PS_1_256 0x0030
95 #define T2_PS_MASK (~T2_PS_1_256)
97 #define T2_32BIT_MODE_ON 0x0008
98 #define T2_32BIT_MODE_OFF 0x0000
99 #define T2_32BIT_MODE_MASK (~T2_32BIT_MODE_ON)
101 #define T2_SOURCE_EXT 0x0002
102 #define T2_SOURCE_INT 0x0000
103 #define T2_SOURCE_MASK (~T2_SOURCE_EXT)
109 #define T3_OFF 0x0000
110 #define T3_OFF_ON_MASK (~T3_ON)
112 #define T3_IDLE_STOP 0x2000
113 #define T3_IDLE_CON 0x0000
114 #define T3_IDLE_MASK (~T3_IDLE_STOP)
116 #define T3_GATE_ON 0x0040
117 #define T3_GATE_OFF 0x0000
118 #define T3_GATE_MASK (~T3_GATE_ON)
120 #define T3_PS_1_1 0x0000
121 #define T3_PS_1_8 0x0010
122 #define T3_PS_1_64 0x0020
123 #define T3_PS_1_256 0x0030
124 #define T3_PS_MASK (~T3_PS_1_256)
126 #define T3_SOURCE_EXT 0x0002
127 #define T3_SOURCE_INT 0x0000
128 #define T3_SOURCE_MASK (~T3_SOURCE_EXT)
134 #define T4_OFF 0x0000
135 #define T4_OFF_ON_MASK (~T4_ON)
137 #define T4_IDLE_STOP 0x2000
138 #define T4_IDLE_CON 0x0000
139 #define T4_IDLE_MASK (~T4_IDLE_STOP)
141 #define T4_GATE_ON 0x0040
142 #define T4_GATE_OFF 0x0000
143 #define T4_GATE_MASK (~T4_GATE_ON)
145 #define T4_PS_1_1 0x0000
146 #define T4_PS_1_8 0x0010
147 #define T4_PS_1_64 0x0020
148 #define T4_PS_1_256 0x0030
149 #define T4_PS_MASK (~T4_PS_1_256)
151 #define T4_32BIT_MODE_ON 0x0008
152 #define T4_32BIT_MODE_OFF 0x0000
153 #define T4_32BIT_MODE_MASK (~T4_32BIT_MODE_ON)
155 #define T4_SOURCE_EXT 0x0002
156 #define T4_SOURCE_INT 0x0000
157 #define T4_SOURCE_MASK (~T4_SOURCE_EXT)
163 #define T5_OFF 0x0000
164 #define T5_OFF_ON_MASK (~T5_ON)
166 #define T5_IDLE_STOP 0x2000
167 #define T5_IDLE_CON 0x0000
168 #define T5_IDLE_MASK (~T5_IDLE_STOP)
170 #define T5_GATE_ON 0x0040
171 #define T5_GATE_OFF 0x0000
172 #define T5_GATE_MASK (~T5_GATE_ON)
174 #define T5_PS_1_1 0x0000
175 #define T5_PS_1_8 0x0010
176 #define T5_PS_1_64 0x0020
177 #define T5_PS_1_256 0x0030
178 #define T5_PS_MASK (~T5_PS_1_256)
180 #define T5_SOURCE_EXT 0x0002
181 #define T5_SOURCE_INT 0x0000
182 #define T5_SOURCE_MASK (~T5_SOURCE_EXT)
188 #define T6_OFF 0x0000
189 #define T6_OFF_ON_MASK (~T6_ON)
191 #define T6_IDLE_STOP 0x2000
192 #define T6_IDLE_CON 0x0000
193 #define T6_IDLE_MASK (~T6_IDLE_STOP)
195 #define T6_GATE_ON 0x0040
196 #define T6_GATE_OFF 0x0000
197 #define T6_GATE_MASK (~T6_GATE_ON)
199 #define T6_PS_1_1 0x0000
200 #define T6_PS_1_8 0x0010
201 #define T6_PS_1_64 0x0020
202 #define T6_PS_1_256 0x0030
203 #define T6_PS_MASK (~T6_PS_1_256)
205 #define T6_32BIT_MODE_ON 0x0008
206 #define T6_32BIT_MODE_OFF 0x0000
207 #define T6_32BIT_MODE_MASK (~T6_32BIT_MODE_ON)
209 #define T6_SOURCE_EXT 0x0002
210 #define T6_SOURCE_INT 0x0000
211 #define T6_SOURCE_MASK (~T6_SOURCE_EXT)
217 #define T7_OFF 0x0000
218 #define T7_OFF_ON_MASK (~T7_ON)
220 #define T7_IDLE_STOP 0x2000
221 #define T7_IDLE_CON 0x0000
222 #define T7_IDLE_MASK (~T7_IDLE_STOP)
224 #define T7_GATE_ON 0x0040
225 #define T7_GATE_OFF 0x0000
226 #define T7_GATE_MASK (~T7_GATE_ON)
228 #define T7_PS_1_1 0x0000
229 #define T7_PS_1_8 0x0010
230 #define T7_PS_1_64 0x0020
231 #define T7_PS_1_256 0x0030
232 #define T7_PS_MASK (~T7_PS_1_256)
234 #define T7_SOURCE_EXT 0x0002
235 #define T7_SOURCE_INT 0x0000
236 #define T7_SOURCE_MASK (~T7_SOURCE_EXT)
242 #define T8_OFF 0x0000
243 #define T8_OFF_ON_MASK (~T8_ON)
245 #define T8_IDLE_STOP 0x2000
246 #define T8_IDLE_CON 0x0000
247 #define T8_IDLE_MASK (~T8_IDLE_STOP)
249 #define T8_GATE_ON 0x0040
250 #define T8_GATE_OFF 0x0000
251 #define T8_GATE_MASK (~T8_GATE_ON)
253 #define T8_PS_1_1 0x0000
254 #define T8_PS_1_8 0x0010
255 #define T8_PS_1_64 0x0020
256 #define T8_PS_1_256 0x0030
257 #define T8_PS_MASK (~T8_PS_1_256)
259 #define T8_32BIT_MODE_ON 0x0008
260 #define T8_32BIT_MODE_OFF 0x0000
261 #define T8_32BIT_MODE_MASK (~T8_32BIT_MODE_ON)
263 #define T8_SOURCE_EXT 0x0002
264 #define T8_SOURCE_INT 0x0000
265 #define T8_SOURCE_MASK (~T8_SOURCE_EXT)
271 #define T9_OFF 0x0000
272 #define T9_OFF_ON_MASK (~T9_ON)
274 #define T9_IDLE_STOP 0x2000
275 #define T9_IDLE_CON 0x0000
276 #define T9_IDLE_MASK (~T9_IDLE_STOP)
278 #define T9_GATE_ON 0x0040
279 #define T9_GATE_OFF 0x0000
280 #define T9_GATE_MASK (~T9_GATE_ON)
282 #define T9_PS_1_1 0x0000
283 #define T9_PS_1_8 0x0010
284 #define T9_PS_1_64 0x0020
285 #define T9_PS_1_256 0x0030
286 #define T9_PS_MASK (~T9_PS_1_256)
288 #define T9_SOURCE_EXT 0x0002
289 #define T9_SOURCE_INT 0x0000
290 #define T9_SOURCE_MASK (~T9_SOURCE_EXT)
302 #if (defined(__dsPIC33E__) || defined(__PIC24E__))
303 #define IC_IDLE_STOP 0x2000
304 #define IC_IDLE_CON 0x0000
305 #define IC_IDLE_MASK (~IC_IDLE_STOP)
307 #define IC_FP_SRC (7 << 10)
308 #define IC_TIMER1_SRC (4 << 10)
309 #define IC_TIMER5_SRC (3 << 10)
310 #define IC_TIMER4_SRC (2 << 10)
311 #define IC_TIMER2_SRC (1 << 10)
312 #define IC_TIMER3_SRC 0x0000
313 #define IC_TIMER_SRC_MASK (~ (7 << 10) )
315 #define IC_INT_4CAPTURE 0x0060
316 #define IC_INT_3CAPTURE 0x0040
317 #define IC_INT_2CAPTURE 0x0020
318 #define IC_INT_1CAPTURE 0x0000
319 #define IC_INT_CAPTURE_MASK (~IC_INT_4CAPTURE)
321 #define IC_INTERRUPT 0x0007
322 #define IC_EVERY_16_RISE_EDGE 0x0005
323 #define IC_EVERY_4_RISE_EDGE 0x0004
324 #define IC_EVERY_RISE_EDGE 0x0003
325 #define IC_EVERY_FALL_EDGE 0x0002
326 #define IC_EVERY_EDGE 0x0001
327 #define IC_INPUTCAP_OFF 0x0000
328 #define IC_CAPTURE_MODE_MASK (~IC_INTERRUPT)
331 #define IC_IC32_ON (0x01 << 8)
332 #define IC_IC32_OFF (0x00 << 8)
333 #define IC_TRIG_MODE (0x01 << 7)
334 #define IC_SYNC_MODE (0x00 << 7)
338 #define IC_SYNCSEL_NOSYNC 0x00
339 #define IC_SYNCSEL_OC1 0x01
340 #define IC_SYNCSEL_OC2 0x02
341 #define IC_SYNCSEL_OC3 0x03
342 #define IC_SYNCSEL_OC4 0x04
343 #define IC_SYNCSEL_PTGO 0x0A
344 #define IC_SYNCSEL_TIMER1 0x0B
345 #define IC_SYNCSEL_TIMER2 0x0C
346 #define IC_SYNCSEL_TIMER3 0x0D
347 #define IC_SYNCSEL_TIMER4 0x0E
348 #define IC_SYNCSEL_TIMER5 0x0F
349 #define IC_SYNCSEL_IC1 0x10
350 #define IC_SYNCSEL_IC2 0x11
351 #define IC_SYNCSEL_IC3 0x12
352 #define IC_SYNCSEL_IC4 0x13
353 #define IC_SYNCSEL_CMP1 0x18
354 #define IC_SYNCSEL_CMP2 0x19
355 #define IC_SYNCSEL_CMP3 0x1A
356 #define IC_SYNCSEL_ADC1 0x1B
357 #define IC_SYNCSEL_CTMU 0x1C
362 #define IC_IDLE_STOP 0x2000
363 #define IC_IDLE_CON 0x0000
364 #define IC_IDLE_MASK (~IC_IDLE_STOP)
366 #define IC_TIMER2_SRC 0x0080
367 #define IC_TIMER3_SRC 0x0000
368 #define IC_TIMER_SRC_MASK (~IC_TIMER2_SRC)
370 #define IC_INT_4CAPTURE 0x0060
371 #define IC_INT_3CAPTURE 0x0040
372 #define IC_INT_2CAPTURE 0x0020
373 #define IC_INT_1CAPTURE 0x0000
374 #define IC_INT_CAPTURE_MASK (~IC_INT_4CAPTURE)
376 #define IC_INTERRUPT 0x0007
377 #define IC_EVERY_16_RISE_EDGE 0x0005
378 #define IC_EVERY_4_RISE_EDGE 0x0004
379 #define IC_EVERY_RISE_EDGE 0x0003
380 #define IC_EVERY_FALL_EDGE 0x0002
381 #define IC_EVERY_EDGE 0x0001
382 #define IC_INPUTCAP_OFF 0x0000
383 #define IC_CAPTURE_MODE_MASK (~IC_INTERRUPT)
396 #if (defined(__dsPIC33E__) || defined(__PIC24E__))
397 #define OC_IDLE_CON 0x0000
398 #define OC_IDLE_STOP 0x2000
399 #define OC_IDLE_MASK (~OC_IDLE_STOP)
400 #define OC_TIMER2_SRC (0 << 10)
401 #define OC_TIMER3_SRC (1 << 10)
402 #define OC_TIMER4_SRC (2 << 10)
403 #define OC_TIMER5_SRC (3 << 10)
404 #define OC_TIMER1_SRC (4 << 10)
405 #define OC_FP_SRC (7 << 10)
408 #define OC_PWM_CENTER_ALIGN 0x0007
409 #define OC_PWM_EDGE_ALIGN 0x0006
410 #define OC_CONTINUE_PULSE 0x0005
411 #define OC_SINGLE_PULSE 0x0004
412 #define OC_TOGGLE_PULSE 0x0003
413 #define OC_HIGH_LOW 0x0002
414 #define OC_LOW_HIGH 0x0001
415 #define OC_OFF 0x0000
416 #define OC_PWM_MODE_MASK (~OC_PWM_FAULT_PIN_ENABLE)
418 #define OC_PWM_FAULT_PIN_ENABLE 0x0007
419 #define OC_PWM_FAULT_PIN_DISABLE 0x0006
422 #define OC_FLTMD_ON (0x01 << 15)
423 #define OC_FLTMD_OFF (0x00 << 15)
424 #define OC_FLTOUT_ON (0x01 << 14)
425 #define OC_FLTOUT_OFF (0x00 << 14)
426 #define OC_FLTTRIEN_ON (0x01 << 13)
427 #define OC_FLTTRIEN_OFF (0x00 << 13)
428 #define OC_OCINV_ON (0x01 << 12)
429 #define OC_OCINV_OFF (0x00 << 12)
431 #define OC_IC32_ON (0x01 << 8)
432 #define OC_IC32_OFF (0x00 << 8)
433 #define OC_TRIG_MODE (0x01 << 7)
434 #define OC_SYNC_MODE (0x00 << 7)
435 #define OC_TRIS_ON (0x01 << 5)
436 #define OC_TRIS_OFF (0x00 << 5)
440 #define OC_SYNCSEL_NOSYNC 0x00
441 #define OC_SYNCSEL_OC1 0x01
442 #define OC_SYNCSEL_OC2 0x02
443 #define OC_SYNCSEL_OC3 0x03
444 #define OC_SYNCSEL_OC4 0x04
445 #define OC_SYNCSEL_PTGO 0x0A
446 #define OC_SYNCSEL_TIMER1 0x0B
447 #define OC_SYNCSEL_TIMER2 0x0C
448 #define OC_SYNCSEL_TIMER3 0x0D
449 #define OC_SYNCSEL_TIMER4 0x0E
450 #define OC_SYNCSEL_TIMER5 0x0F
451 #define OC_SYNCSEL_IC1 0x10
452 #define OC_SYNCSEL_IC2 0x11
453 #define OC_SYNCSEL_IC3 0x12
454 #define OC_SYNCSEL_IC4 0x13
455 #define OC_SYNCSEL_CMP1 0x18
456 #define OC_SYNCSEL_CMP2 0x19
457 #define OC_SYNCSEL_CMP3 0x1A
458 #define OC_SYNCSEL_ADC1 0x1B
459 #define OC_SYNCSEL_CTMU 0x1C
460 #define OC_SYNCSEL_INT1 0x1D
461 #define OC_SYNCSEL_INT2 0x1E
462 #define OC_SYNCSEL_OCxRS 0x1F
466 #define OC_IDLE_CON 0x0000
467 #define OC_IDLE_STOP 0x2000
468 #define OC_IDLE_MASK (~OC_IDLE_STOP)
471 #define OC_TIMER2_SRC 0x0000
472 #define OC_TIMER3_SRC 0x0008
473 #define OC_TIMER_SRC_MASK (~OC_TIMER3_SRC)
475 #define OC_PWM_FAULT_PIN_ENABLE 0x0007
476 #define OC_PWM_FAULT_PIN_DISABLE 0x0006
477 #define OC_CONTINUE_PULSE 0x0005
478 #define OC_SINGLE_PULSE 0x0004
479 #define OC_TOGGLE_PULSE 0x0003
480 #define OC_HIGH_LOW 0x0002
481 #define OC_LOW_HIGH 0x0001
482 #define OC_OFF 0x0000
483 #define OC_PWM_MODE_MASK (~OC_PWM_FAULT_PIN_ENABLE)