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esos
include
pic24
esos_pic24_spi.h
Go to the documentation of this file.
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/*
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* "Copyright (c) 2008 Robert B. Reese, Bryan A. Jones, J. W. Bruce ("AUTHORS")"
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* All rights reserved.
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* (R. Reese, reese_AT_ece.msstate.edu, Mississippi State University)
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* (B. A. Jones, bjones_AT_ece.msstate.edu, Mississippi State University)
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* (J. W. Bruce, jwbruce_AT_ece.msstate.edu, Mississippi State University)
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*
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* Permission to use, copy, modify, and distribute this software and its
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* documentation for any purpose, without fee, and without written agreement is
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* hereby granted, provided that the above copyright notice, the following
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* two paragraphs and the authors appear in all copies of this software.
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*
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* IN NO EVENT SHALL THE "AUTHORS" BE LIABLE TO ANY PARTY FOR
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* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
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* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE "AUTHORS"
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* HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* THE "AUTHORS" SPECIFICALLY DISCLAIMS ANY WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
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* ON AN "AS IS" BASIS, AND THE "AUTHORS" HAS NO OBLIGATION TO
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* PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
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*
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* Please maintain this header in its entirety when copying/modifying
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* these files.
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*
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*
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*/
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#ifndef _ESOS_PIC24_SPI_H
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#define _ESOS_PIC24_SPI_H
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/**
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* \addtogroup ESOS_SPI_Service
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* @{
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*/
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// Documentation for this file. If the \file tag isn't present,
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// this file won't be documented.
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/** \file
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* This file contains routines which se SPI on the Microchip PIC24 MCU.
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*/
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/* I N C L U D E S **********************************************************/
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#include "
esos.h
"
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#include "
esos_pic24.h
"
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/* D E F I N I T I O N S ****************************************************/
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/*
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The following macros are a subset of the AND/OR macros found in the
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the MPLAB C30/src/peripheral_24F/spi.h file and placed
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in this header for use solely and exclusively on Microchip
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PICmicro Microcontroller products as
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specified in the MPLAB C30/src/peripheral_24F/spi.h header.
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*/
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/* SPIXCON1: SPIx CONTROL REGISTER 1 */
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#define DISABLE_SCK_PIN 0x1000
/* SCK pin is not used by module */
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#define ENABLE_SCK_PIN 0x0000
/* SCK pin is used by module */
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#define SCK_PIN_MASK (~DISABLE_SCK_PIN)
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#define DISABLE_SDO_PIN 0x0800
/* SDO pin is not used by module */
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#define ENABLE_SDO_PIN 0x0000
/* SDO pin is used by module */
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#define SDO_PIN_MASK (~DISABLE_SDO_PIN)
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#define SPI_MODE16_ON 0x0400
/* Communication is word wide */
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#define SPI_MODE8_ON 0x0000
/* Communication is byte wide */
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#define SPI_MODE_MASK (~SPI_MODE16_ON)
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#define SPI_SMP_ON 0x0200
/* Input data sampled at end of data output time */
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#define SPI_SMP_OFF 0x0000
/* Input data sampled at middle of data output time */
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#define SPI_SMP_MASK (~SPI_SMP_ON)
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#define SPI_CKE_ON 0x0100
/* Transmit happens from active clock state to idle clock state*/
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#define SPI_CKE_OFF 0x0000
/* Transmit happens on transition from idle clock state to active clock state */
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#define SPI_CKE_MASK (~SPI_CKE_ON)
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#define SLAVE_ENABLE_ON 0x0080
/* Slave Select enbale */
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#define SLAVE_ENABLE_OFF 0x0000
/* Slave Select not used by module */
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#define SLAVE_ENABLE_MASK (~SLAVE_ENABLE_ON)
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#define CLK_POL_ACTIVE_LOW 0x0040
/* Idle state for clock is high, active is low */
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#define CLK_POL_ACTIVE_HIGH 0x0000
/* Idle state for clock is low, active is high */
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#define CLK_POL_ACTIVE_MASK (~CLK_POL_ACTIVE_LOW)
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#define MASTER_ENABLE_ON 0x0020
/* Master Mode */
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#define MASTER_ENABLE_OFF 0x0000
/* Slave Mode */
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#define MASTER_ENABLE_MASK (~MASTER_ENABLE_ON)
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#define SEC_PRESCAL_1_1 0x001c
/* Secondary Prescale 1:1 */
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#define SEC_PRESCAL_2_1 0x0018
/* Secondary Prescale 2:1 */
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#define SEC_PRESCAL_3_1 0x0014
/* Secondary Prescale 3:1 */
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#define SEC_PRESCAL_4_1 0x0010
/* Secondary Prescale 4:1 */
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#define SEC_PRESCAL_5_1 0x000c
/* Secondary Prescale 5:1 */
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#define SEC_PRESCAL_6_1 0x0008
/* Secondary Prescale 6:1 */
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#define SEC_PRESCAL_7_1 0x0004
/* Secondary Prescale 7:1 */
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#define SEC_PRESCAL_8_1 0x0000
/* Secondary Prescale 8:1 */
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#define SEC_PRESCAL_MASK (~SEC_PRESCAL_1_1)
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#define PRI_PRESCAL_1_1 0x0003
/* Primary Prescale 1:1 */
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#define PRI_PRESCAL_4_1 0x0002
/* Primary Prescale 4:1 */
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#define PRI_PRESCAL_16_1 0x0001
/* Primary Prescale 16:1 */
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#define PRI_PRESCAL_64_1 0x0000
/* Primary Prescale 64:1 */
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#define PRI_PRESCAL_MASK (~PRI_PRESCAL_1_1)
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/* SPIxSTAT REGISTER */
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#define SPI_ENABLE 0x8000
/* Enable module */
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#define SPI_DISABLE 0x0000
/* Disable module */
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#define SPI_ENBL_DSBL_MASK (~SPI_ENABLE)
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#define SPI_IDLE_STOP 0x2000
/* Discontinue module operation in idle mode */
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#define SPI_IDLE_CON 0x0000
/* Continue module operation in idle mode */
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#define SPI_IDLE_MASK (~SPI_IDLE_STOP)
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#define SPI_RX_OVFLOW 0x0040
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#define SPI_RX_OVFLOW_CLR 0x0000
/* Clear receive overflow bit */
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#define SPI_TX_BUFFER_FULL 0x0002
/* TX not started yet; SPIxTXB is full */
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#define SPI_TX_BUFFER_FULL_CLR (~SPI_TX_BUFFER_FULL)
/* TX underway; SPIxTXB is empty */
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#define SPI_RX_BUFFER_FULL 0x0001
/* RX complete; SPIxRXB is full */
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#define SPI_RX_BUFFER_FULL_CLR (~SPI_RX_BUFFER_FULL)
/* RX complete; SPIxRXB is full */
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/* SPIxCON2: SPIx CONTROL REGISTER 2 */
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#define FRAME_ENABLE_ON 0x8000
/* Frame SPI support enable */
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#define FRAME_ENABLE_OFF 0x0000
/* Frame SPI support Disable */
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#define FRAME_ENABLE_MASK (~FRAME_ENABLE_ON)
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#define FRAME_SYNC_INPUT 0x4000
/* Frame sync pulse Input (slave) */
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#define FRAME_SYNC_OUTPUT 0x0000
/* Frame sync pulse Output (master)*/
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#define FRAME_SYNC_MASK (~FRAME_SYNC_INPUT)
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#define FRAME_SYNC_ACTIVE_HIGH 0x2000
/* Frame sync pulse Input (slave) */
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#define FRAME_SYNC_ACTIVE_LOW 0x0000
/* Frame sync pulse Output (master)*/
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#define FRAME_SYNC_POL_MASK (~FRAME_SYNC_ACTIVE_HIGH)
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#define SPI_FRM_PULSE_FIRST_CLK 0x0002
/* frame pulse coincides with the first bit clock */
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#define SPI_FRM_PULSE_PREV_CLK 0x0000
/* frame pulse precedes the first bit clock */
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#define SPI_FRM_PULSE_MASK (~SPI_FRM_PULSE_FIRST_CLK)
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#define SPI_ENH_BUFF_ENABLE 0x0001
/* enable enhanced buffer */
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#define SPI_ENH_BUFF_DISABLE 0x0000
/* disable enhanced buffer */
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#define SPI_ENH_BUFF_MASK (~SPI_ENH_BUFF_ENABLE)
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/* E X T E R N S ************************************************************/
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extern
struct
stTask __stChildTaskSPI;
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extern
uint16_t __esos_spi_u16s[2];
// used to store arguments
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/* M A C R O S **************************************************************/
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#define ESOS_TASK_WAIT_ON_AVAILABLE_SPI() \
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do { \
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ESOS_TASK_WAIT_WHILE(__esos_IsSystemFlagSet(__ESOS_SYS_SPI_IS_BUSY)); \
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__esos_SetSystemFlag(__ESOS_SYS_SPI_IS_BUSY); \
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}while(0)
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#define ESOS_TASK_SIGNAL_AVAILABLE_SPI() __esos_ClearSystemFlag(__ESOS_SYS_SPI_IS_BUSY)
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/**
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Transaction: Write 1 (ONE) "word" stored in variable \em u16_d1 to SPI device.
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\param u16_d1 Variable containing word (byte or 16-bits) to write
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\note Assumes SPI peripheral has been properly configured.
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\note SPI peripheral configuration determines whether 8 or 16 bits are written.
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\sa ESOS_TASK_WAIT_ON_WRITE2SPI1
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\sa ESOS_TASK_WAIT_ON_WRITENSPI1
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\sa ESOS_TASK_WAIT_ON_XFERNSPI1
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\hideinitializer
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*/
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#define ESOS_TASK_WAIT_ON_WRITE1SPI1(u16_d1 ) \
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do{ \
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__esos_spi_u16s[0] = (uint16_t) (u16_d1); \
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ESOS_TASK_SPAWN_AND_WAIT( (ESOS_TASK_HANDLE)&__stChildTaskSPI, __esos_pic24_xferNSPI1, &__esos_spi_u16s[0], NULLPTR, 1 ); \
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}while(0)
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// We need a 2-byte array to be able to use the buffer.
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// Otherwise, we'd need two writeN calls, which require
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// child tasks, i.e. code size grows
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/**
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Transaction: Write 2 (TWO) "words" (bytes or 16-bits) stored in variables \em u16_d1 and \em u16_d2 to SPI device.
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\param u16_d1 Variable containing first byte to write
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\param u16_d2 Variable containing second byte to write
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\note Assumes SPI peripheral has been properly configured.
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\note SPI peripheral configuration determines whether 8 or 16 bits are written.
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\sa ESOS_TASK_WAIT_ON_WRITE1SPI1
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\sa ESOS_TASK_WAIT_ON_WRITENSPI1
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\sa ESOS_TASK_WAIT_ON_XFERNSPI1
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\hideinitializer
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*/
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#define ESOS_TASK_WAIT_ON_WRITE2SPI1(u16_d1, u16_d2 ) \
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do{ \
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__esos_spi_u16s[0] = (uint16_t) (u16_d1); \
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__esos_spi_u16s[1] = (uint16_t) (u16_d2); \
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ESOS_TASK_SPAWN_AND_WAIT( (ESOS_TASK_HANDLE)&__stChildTaskSPI, __esos_pic24_xferNSPI1, &__esos_spi_u16s[0], NULLPTR, 2 ); \
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}while(0)
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/**
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Transaction: Write \em u16_cnt "words" (bytes or 16-bits) to SPI device
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\param pu16_out Pointer to buffer containing words to send
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\param u16_cnt Number of bytes to send
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\note Assumes SPI peripheral has been properly configured.
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\note SPI peripheral configuration determines whether 8 or 16 bits are written.
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\sa ESOS_TASK_WAIT_ON_WRITE1SPI1
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\sa ESOS_TASK_WAIT_ON_WRITE2SPI1
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\sa ESOS_TASK_WAIT_ON_XFERNSPI1
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\hideinitializer
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*/
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#define ESOS_TASK_WAIT_ON_WRITENSPI1( pu16_out, u16_cnt ) \
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ESOS_TASK_SPAWN_AND_WAIT( (ESOS_TASK_HANDLE)&__stChildTaskSPI, __esos_pic24_xferNSPI1, (pu16_out), NULLPTR, (u16_cnt) )
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/**
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Transaction: Transfer (Read and write SPI simultaneously) \em u16_cnt "words" (bytes or 16-bits) to SPI device
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\param pu16_out Pointer to buffer containing words to send
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\param pu16_in Pointer to buffer to catch incoming words
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\param u16_cnt Number of bytes to send
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\note Assumes SPI peripheral has been properly configured.
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\note SPI peripheral configuration determines whether 8 or 16 bits are written.
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\note Assumes that both incoming and outgoing buffers are properly sized and available.
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\sa ESOS_TASK_WAIT_ON_WRITE1SPI1
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\sa ESOS_TASK_WAIT_ON_WRITE2SPI1
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\sa ESOS_TASK_WAIT_ON_WRITENSPI1
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\sa ESOS_TASK_WAIT_ON_READ1SPI1
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\sa ESOS_TASK_WAIT_ON_READ2SPI1
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\sa ESOS_TASK_WAIT_ON_READNSPI1
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\hideinitializer
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*/
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#define ESOS_TASK_WAIT_ON_XFERNSPI1( pu16_out, pu16_in, u16_cnt ) \
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ESOS_TASK_SPAWN_AND_WAIT( (ESOS_TASK_HANDLE)&__stChildTaskSPI, __esos_pic24_xferNSPI1, (pu16_out), (pu16_in), (u16_cnt) )
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/**
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Transaction: Read 1 (ONE) "word" from SPI device and stores result in variable \em u16_d1
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\param u16_d1 Variable containing word (byte or 16-bits) to hold read results
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\note Assumes SPI peripheral has been properly configured.
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\note SPI peripheral configuration determines whether 8 or 16 bits are written.
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\note This routine writes ZEROES to SPI device during reads
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\sa ESOS_TASK_WAIT_ON_READ2SPI1
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\sa ESOS_TASK_WAIT_ON_READNSPI1
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\sa ESOS_TASK_WAIT_ON_XFERNSPI1
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\hideinitializer
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*/
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#define ESOS_TASK_WAIT_ON_READ1SPI1(u16_d1 ) \
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do{ \
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ESOS_TASK_SPAWN_AND_WAIT( (ESOS_TASK_HANDLE)&__stChildTaskSPI, __esos_pic24_xferNSPI1, NULLPTR, &__esos_spi_u16s[0], 1 ); \
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(u16_d1) = __esos_spi_u16s[0]; \
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}while(0)
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/**
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Transaction: Read 2 (TWO) "words" (bytes or 16-bits) from SPI device. Stores results in variables \em u16_d1 and \em u16_d2
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\param u16_d1 Variable containing first word/byte read
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\param u16_d2 Variable containing second word/byte read
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\note Assumes SPI peripheral has been properly configured.
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\note SPI peripheral configuration determines whether 8 or 16 bits are written.
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\note This routine writes ZEROES to SPI device during reads
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\sa ESOS_TASK_WAIT_ON_READ1SPI1
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\sa ESOS_TASK_WAIT_ON_READNSPI1
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\sa ESOS_TASK_WAIT_ON_XFERNSPI1
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\hideinitializer
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*/
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#define ESOS_TASK_WAIT_ON_READ2SPI1(u16_d1, u16_d2) \
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do{ \
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ESOS_TASK_SPAWN_AND_WAIT( (ESOS_TASK_HANDLE)&__stChildTaskSPI, __esos_pic24_xferNSPI1, NULLPTR, &__esos_spi_u16s[0], 2 ); \
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(u16_d1) = __esos_spi_u16s[0]; \
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(u16_d2) = __esos_spi_u16s[1]; \
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}while(0)
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/**
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Transaction: Reads \em u16_cnt "words" (bytes or 16-bits) from SPI device. Results are written to buffer pointed to by \em pu16_d
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\param pu16_in Pointer to buffer to catch read results
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\param u16_cnt Number of bytes to read
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\note Assumes SPI peripheral has been properly configured.
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\note SPI peripheral configuration determines whether 8 or 16 bits are written.
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\note This routine writes ZEROES to SPI device during reads
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\sa ESOS_TASK_WAIT_ON_READ1SPI1
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\sa ESOS_TASK_WAIT_ON_READ2SPI1
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\sa ESOS_TASK_WAIT_ON_XFERNSPI1
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\hideinitializer
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*/
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#define ESOS_TASK_WAIT_ON_READNSPI1( pu16_in, u16_cnt ) \
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ESOS_TASK_SPAWN_AND_WAIT( (ESOS_TASK_HANDLE)&__stChildTaskSPI, __esos_pic24_xferNSPI1, NULLPTR, (pu16_in), (u16_cnt) )
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/* P U B L I C P R O T O T Y P E S *****************************************/
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ESOS_CHILD_TASK
( __esos_pic24_xferNSPI1, uint16_t* pu16_out, uint16_t* pu16_in, uint16_t u16_cnt);
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/** @} */
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#endif // end ESOS_PIC24_SPI_H
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