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15 #define DMA_MODULE_ON 0x8000
16 #define DMA_MODULE_OFF 0x0000
17 #define DMA_MODULE_MASK (~DMA_MODULE_ON)
19 #define DMA_SIZE_BYTE 0x4000
20 #define DMA_SIZE_WORD 0x0000
21 #define DMA_SIZE_MASK (~DMA_SIZE_BYTE);
23 #define DMA_DIR_WRITE_PERIPHERAL 0x2000
24 #define DMA_DIR_READ_PERIPHERAL 0x0000
25 #define DMA_DIR_MASK (~DMA_DIR_WRITE_PERIPHERAL)
27 #define DMA_INTERRUPT_HALF 0x1000
28 #define DMA_INTERRUPT_FULL 0x0000
29 #define DMA_INTERRUPT_MASK (~DMA_INTERRUPT_HALF)
31 #define DMA_NULLW_ON 0x0800
32 #define DMA_NULLW_OFF 0x0000
33 #define DMA_NULLW_MASK (~DMA_NULLW_ON)
35 #define DMA_AMODE_PERIPHERAL_INDIRECT 0x0020
36 #define DMA_AMODE_REGISTER_INDIRECT 0x0010
37 #define DMA_AMODE_REGISTER_POSTINC 0x0000
38 #define DMA_AMODE_MASK (~DMA_AMODE_PERIPHERAL_INDIRECT)
41 #define DMA_MODE_ONE_SHOT_PING_PONG 0x0003
42 #define DMA_MODE_CONTINUOUS_PING_PONG 0x0002
43 #define DMA_MODE_ONE_SHOT 0x0001
44 #define DMA_MODE_CONTINUOUS 0x0000
45 #define DMA_MODE_MASK (~DMA_MODE_ONE_SHOT_PING_PONG)
48 #define DMA_IRQ_INT0 0x0000
49 #define DMA_IRQ_IC1 0x0001
50 #define DMA_IRQ_OC1 0x0002
51 #define DMA_IRQ_IC2 0x0005
52 #define DMA_IRQ_OC2 0x0006
53 #define DMA_IRQ_IC3 0x0025
54 #define DMA_IRQ_OC3 0x0019
55 #define DMA_IRQ_IC4 0x0026
56 #define DMA_IRQ_OC4 0x001A
57 #define DMA_IRQ_TMR2 0x0007
58 #define DMA_IRQ_TMR3 0x0008
59 #define DMA_IRQ_TMR4 0x001B
60 #define DMA_IRQ_TMR5 0x001C
61 #define DMA_IRQ_SPI1 0x000A
62 #define DMA_IRQ_SPI2 0x0021
63 #define DMA_IRQ_SPI3 0x005B
64 #define DMA_IRQ_SPI4 0x007B
65 #define DMA_IRQ_U1RX 0x000B
66 #define DMA_IRQ_U1TX 0x000C
67 #define DMA_IRQ_U2RX 0x001E
68 #define DMA_IRQ_U2TX 0x001F
69 #define DMA_IRQ_U3RX 0x0052
70 #define DMA_IRQ_U3TX 0x0053
71 #define DMA_IRQ_U4RX 0x0058
72 #define DMA_IRQ_U4TX 0x0059
73 #define DMA_IRQ_ADC1 0x000D
74 #define DMA_IRQ_ADC2 0x0015
75 #define DMA_IRQ_ECAN1RX 0x0022
76 #define DMA_IRQ_ECAN2RX 0x0037
77 #define DMA_IRQ_ECAN1TX 0x0046
78 #define DMA_IRQ_ECAN2TX 0x0047
79 #define DMA_IRQ_PMP 0x002D
82 #define DMA_PAD_IC1BUF 0x0144
83 #define DMA_PAD_OC1R 0x0906
84 #define DMA_PAD_OC1RS 0x0904
85 #define DMA_PAD_IC2BUF 0x014C
86 #define DMA_PAD_OC2R 0x0910
87 #define DMA_PAD_OC2RS 0x090E
88 #define DMA_PAD_IC3BUF 0x0154
89 #define DMA_PAD_OC3R 0x091A
90 #define DMA_PAD_OC3RS 0x0918
91 #define DMA_PAD_IC4BUF 0x015C
92 #define DMA_PAD_OC4R 0x0924
93 #define DMA_PAD_OC4RS 0x0922
94 #define DMA_PAD_SPI1BUF 0x0248
95 #define DMA_PAD_SPI2BUF 0x0268
96 #define DMA_PAD_SPI3BUF 0x02A8
97 #define DMA_PAD_SPI4BUF 0x02C8
98 #define DMA_PAD_U1RXREG 0x0226
99 #define DMA_PAD_U1TXREG 0x0224
100 #define DMA_PAD_U2RXREG 0x0236
101 #define DMA_PAD_U2TXREG 0x0234
102 #define DMA_PAD_U3RXREG 0x0256
103 #define DMA_PAD_U3TXREG 0x0254
104 #define DMA_PAD_U4RXREG 0x02B6
105 #define DMA_PAD_U4TXREG 0x02B4
106 #define DMA_PAD_ADC1BUF0 0x0300
107 #define DMA_PAD_ADC2BUF0 0x0340
108 #define DMA_PAD_C1RXD 0x0440
109 #define DMA_PAD_C2RXD 0x0540
110 #define DMA_PAD_C1TXD 0x0442
111 #define DMA_PAD_C2TXD 0x0542
112 #define DMA_PAD_PMDIN1 0x0608