PIC24 Support Libraries
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pic24_configbits.c
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1 /*
2  * "Copyright (c) 2008 Robert B. Reese, Bryan A. Jones, J. W. Bruce ("AUTHORS")"
3  * All rights reserved.
4  * (R. Reese, reese_AT_ece.msstate.edu, Mississippi State University)
5  * (B. A. Jones, bjones_AT_ece.msstate.edu, Mississippi State University)
6  * (J. W. Bruce, jwbruce_AT_ece.msstate.edu, Mississippi State University)
7  *
8  * Permission to use, copy, modify, and distribute this software and its
9  * documentation for any purpose, without fee, and without written agreement is
10  * hereby granted, provided that the above copyright notice, the following
11  * two paragraphs and the authors appear in all copies of this software.
12  *
13  * IN NO EVENT SHALL THE "AUTHORS" BE LIABLE TO ANY PARTY FOR
14  * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
15  * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE "AUTHORS"
16  * HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17  *
18  * THE "AUTHORS" SPECIFICALLY DISCLAIMS ANY WARRANTIES,
19  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
20  * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
21  * ON AN "AS IS" BASIS, AND THE "AUTHORS" HAS NO OBLIGATION TO
22  * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
23  *
24  * Please maintain this header in its entirety when copying/modifying
25  * these files.
26  *
27  *
28  */
29 
30 
31 // Documentation for this file. If the \file tag isn't present,
32 // this file won't be documented.
33 /** \file
34  * This file contains configuration bit settings. Important points on the
35  * syntax used:
36  * - The "functions" below are actually macros which set
37  * these configuration bits. For more details, see
38  * the chip-specific include file, such as <code>p24HJ12GP201.h</code>
39  * in <code>C:\\Program Files\\Microchip\\MPLAB C30\\support\\h</code>,
40  * <!-- Note: extra \\ needed to prevent Doxygen errors, but
41  * these are not actually part of the path.
42  * --> which contain macros (starting on line 2843) to ease setting
43  * configuration bits.
44  * - Instead of ORing bits, AND them: use for example
45  * <code>GSS_OFF & GCP_OFF</code>, NOT
46  * <code>GSS_OFF | GCP_OFF</code>.
47  * - Only one invocation of each config register
48  * should appear in a project, at the top of a C
49  * source file (outside of any function).
50  * - All possible configuration options are listed; the
51  * option currently in use is indicated by an arrow
52  * <code>--></code> next to the setting.
53  * - This file contains configuration settings for some of the
54  * PIC24 family of chips. To change or add support for a new
55  * chip, examine the include-file documentation and read the
56  * FRM documentation on config bits plus the chip-specific
57  * documentation on config bits.
58  *
59  * Note on clock choice: The processor is configured to always
60  * start up with the FRC, rather than what it will use after
61  * clock configuration. This guarantees a working clock at
62  * power-up, which can then be changed by the bootloader / user
63  * code / etc.
64  */
65 
66 #include "pic24_clockfreq.h"
67 
68 #ifndef IOL1WAY_OFF
69 // If this device dones't have the IOL1WAY config bit, define the OFF value
70 // to have no effect (to be all 1s, since config bits are ANDed together).
71 # define IOL1WAY_OFF 0xFFFF
72 #endif
73 
74 #ifndef OSCIOFNC_OFF
75 // Same as above for OSCIOFNC.
76 # define OSCIOFNC_OFF 0xFFFF
77 #endif
78 
79 #ifdef BOOTLOADER
80 // POSCMD_XT: Select bootloader config bits which allow user code to optionally
81 // use an XT oscillator. Change this for an HS crystal or an external clock (EC).
82 //
83 // OSCIOFNC_OFF: Reserve OSC2 as a potential crystal pin, instead of making it
84 // a digital I/O pin.
85 # define OSCPIN_CONFIG (OSCIOFNC_OFF & POSCMD_XT)
86 #else
87 // Enable/disable OSC IO pins based on oscillator selection.
88 # if POSCMD_SEL == POSCMD_NONE
89 // Make the OSC2 pin a digital I/O.
90 # define OSCPIN_CONFIG (OSCIOFNC_ON & POSCMD_NONE)
91 # else
92 // Reserve the OSC pins for use with an oscillator (HS and XT modes) or
93 // have it output the clock (EC mode).
94 # define OSCPIN_CONFIG (OSCIOFNC_OFF & POSCMD_SEL)
95 # endif
96 #endif
97 
98 
99 
100 /// \name PIC24H configuration bits
101 //@{
102 #if defined(__PIC24HJ12GP202__) || \
103  defined(__PIC24HJ12GP201__) || \
104  defined(__PIC24HJ32GP202__) || \
105  defined(__PIC24HJ32GP202__) || \
106  defined(__PIC24HJ16GP304__) || \
107  defined(__DOXYGEN__) // NOTE: DOXYGEN only used for documentation generation
108 
109 
110 /** FBS: Boot Code Segment Configuration Register
111  ** \code
112  ** Boot Segment Program Memory:
113  ** BSS_HIGH_LARGE_BOOT_CODE High Security Lar Boot Flash
114  ** BSS_LARGE_FLASH_HIGH High Security Lar Boot Flash
115  ** BSS_HIGH_MEDIUM_BOOT_CODE High Security Med Boot Flash
116  ** BSS_MEDIUM_FLASH_HIGH High Security Med Boot Flash
117  ** BSS_HIGH_SMALL_BOOT_CODE High Security Small Boot Flash
118  ** BSS_SMALL_FLASH_HIGH High Security Small Boot Flash
119  ** BSS_LARGE_FLASH_STD Standard Security Lar Boot Flash
120  ** BSS_STRD_LARGE_BOOT_CODE Standard Security Lar Boot Flash
121  ** BSS_MEDIUM_FLASH_STD Standard Security Med Boot Flash
122  ** BSS_STRD_MEDIUM_BOOT_CODE Standard Security Med Boot Flash
123  ** BSS_SMALL_FLASH_STD Standard Security Small Boot Flash
124  ** BSS_STRD_SMALL_BOOT_CODE Standard Security Small Boot Flash
125  ** BSS_NO_BOOT_CODE No Boot Segment Program Memory
126  ** BSS_NO_FLASH No Boot Segment Program Memory
127  **
128  ** Write Protect :
129  ** BWRP_WRPROTECT_ON Enabled
130  ** -->BWRP_WRPROTECT_OFF Disabled
131  ** Note: since this is off, size bits above don't matter.
132  \endcode
133  */
134 _FBS(BWRP_WRPROTECT_OFF);
135 
136 /* FSS: Secure Code Segment Configuration Register
137 ** Not present on this chip.
138 */
139 
140 /** FGS: General Code Segment Configuration Register
141  ** \code
142  ** Code Protect:
143  ** GSS_HIGH high security protect on
144  ** GSS_STD standard security code protect on
145  ** -->GSS_OFF code protect off
146  **
147  ** Code Protect:
148  ** GCP_ON Enabled
149  ** -->GCP_OFF Disabled
150  ** These bits aren't mentioned in the manuals!
151  ** Probably a typo in the .h file.
152  **
153  ** Write Protect:
154  ** GWRP_ON Enabled
155  ** -->GWRP_OFF Disabled
156  **
157  \endcode
158  */
159 _FGS(GSS_OFF & GCP_OFF & GWRP_OFF);
160 
161 
162 /** FOSCSEL: Oscillator Source Selection Register
163  ** \code
164  ** Oscillator Source Selection:
165  ** -->FNOSC_FRC Fast RC oscillator
166  ** FNOSC_FRCPLL Fast RC oscillator w/ divide and PLL
167  ** FNOSC_PRI Primary oscillator (XT, HS, EC)
168  ** FNOSC_PRIPLL Primary oscillator (XT, HS, EC) w/ PLL
169  ** FNOSC_SOSC Secondary oscillator
170  ** FNOSC_LPRC Low power RC oscillator
171  ** FNOSC_FRCDIV16 Fast RC oscillator w/ divide by 16
172  ** FNOSC_LPRCDIVN Low power Fast RC oscillator w/divide by N
173  **
174  ** Two-speed Oscillator Startup :
175  ** IESO_ON Enabled
176  ** -->IESO_OFF Disabled
177  **
178  \endcode
179  */
180 _FOSCSEL(FNOSC_FRC & IESO_OFF);
181 
182 /** FOSC: Oscillator Configuration Register
183  ** \code
184  ** Clock switching and clock monitor:
185  ** FCKSM_CSECME Both enabled
186  ** -->FCKSM_CSECMD Only clock switching enabled
187  ** FCKSM_CSDCMD Both disabled
188  ** Clock switching must be enabled to allow a switch
189  ** up to the PLL.
190  **
191  ** Single configuration for remappable I/O:
192  ** -->IOL1WAY_OFF Disabled
193  ** IOL1WAY_ON Enabled
194  **
195  ** OSC2 Pin function:
196  ** -->OSCIOFNC_ON Digital I/O
197  ** OSCIOFNC_OFF OSC2 is clock O/P
198  ** Note: this frees up OSC1 for digitial I/O when
199  ** not in HS or XT modes (per POSCMD_SEL).
200  **
201  ** Oscillator Selection:
202  ** Taken from POSCMD_SEL
203  **
204  \endcode
205  */
206 
207 _FOSC(FCKSM_CSECMD & IOL1WAY_OFF & OSCPIN_CONFIG );
208 
209 
210 
211 /** FWDT: Watchdog Timer Configuration Register
212  ** \code
213  ** Watchdog Timer:
214  ** -->FWDTEN_OFF Disabled
215  ** FWDTEN_ON Enabled
216  **
217  ** Windowed WDT:
218  ** WINDIS_ON Enabled
219  ** -->WINDIS_OFF Disabled
220  **
221  ** Watchdog prescaler:
222  ** WDTPRE_PR32 1:32
223  ** -->WDTPRE_PR128 1:128
224  **
225  ** Watchdog postscaler:
226  ** WDTPOST_PS1 1:1
227  ** WDTPOST_PS2 1:2
228  ** WDTPOST_PS4 1:4
229  ** WDTPOST_PS8 1:8
230  ** WDTPOST_PS16 1:16
231  ** WDTPOST_PS32 1:32
232  ** WDTPOST_PS64 1:64
233  ** WDTPOST_PS128 1:128
234  ** WDTPOST_PS256 1:256
235  ** -->WDTPOST_PS512 1:512
236  ** WDTPOST_PS1024 1:1,024
237  ** WDTPOST_PS2048 1:2,048
238  ** WDTPOST_PS4096 1:4,096
239  ** WDTPOST_PS8192 1:8,192
240  ** WDTPOST_PS16384 1:16,384
241  ** WDTPOST_PS32768 1:32,768
242  ** 128*512 = 65536 ~ 0.5 Hz ~ 2 secs (WDT is ~ 32 KHz)
243  \endcode
244  */
245 _FWDT(FWDTEN_OFF & WINDIS_OFF & WDTPRE_PR128 & WDTPOST_PS512);
246 
247 /** FPOR: POR Configuration Register
248  ** \code
249  ** Power-on Reset Value:
250  ** FPWRT_PWR1 Disabled
251  ** FPWRT_PWR2 2ms
252  ** FPWRT_PWR4 4ms
253  ** FPWRT_PWR8 8ms
254  ** -->FPWRT_PWR16 16ms
255  ** FPWRT_PWR32 32ms
256  ** FPWRT_PWR64 64ms
257  ** FPWRT_PWR128 128ms
258  **
259  ** Aletrnate I2C Pins:
260  ** ALTI2C_ON I2C mapped to ASDA1/ASCL1
261  ** -->ALTI2C_OFF I2C mapped to SDA1/SCL1
262  **
263  \endcode
264  */
265 _FPOR(FPWRT_PWR16 & ALTI2C_OFF);
266 
267 /** FICD: the debugger configuration word.
268  ** \code
269  ** JTAG Enable Bit:
270  ** -->JTAGEN_OFF JTAG is disabled
271  ** JTAGEN_ON JTAG is enabled
272  ** The one important thing in this
273  ** field for normal use is to disable the JTAG mode. If you do not
274  ** disable the JTAG mode, then the TDI, TMS, TDO, TCK pins are
275  ** not usable which severly limits the GP202/GP201 processors.
276  **
277  ** ICD communication channel select bits:
278  ** ICS_NONE Reserved
279  ** ICS_PGD3 communicate on PGC3/EMUC3 and PGD3/EMUD3
280  ** ICS_PGD2 communicate on PGC2/EMUC2 and PGD2/EMUD2
281  ** -->ICS_PGD1 communicate on PGC1/EMUC1 and PGD1/EMUD1
282  **
283  \endcode
284  */
285 _FICD(JTAGEN_OFF & ICS_PGD1);
286 
287 ///\cond doxygen_ignore
288 #define CONFIG_BITS_DEFINED
289 ///\endcond
290 
291 #endif // #ifdef (lots of PIC24H devices)
292 //@}
293 
294 
295 #if defined(EXPLORER16_100P) && defined(__PIC24HJ256GP610__)
296 _FBS(BWRP_WRPROTECT_OFF);
297 _FGS(GSS_OFF & GCP_OFF & GWRP_OFF);
298 _FOSCSEL(FNOSC_FRC & IESO_OFF);
299 _FOSC(FCKSM_CSECMD & OSCPIN_CONFIG );
300 _FWDT(FWDTEN_OFF & WINDIS_OFF & WDTPRE_PR128 & WDTPOST_PS512);
301 _FPOR(FPWRT_PWR16);
302 _FICD(JTAGEN_OFF & ICS_PGD1);
303 #define CONFIG_BITS_DEFINED
304 #endif
305 
306 
307 /// \name PIC24F configuration bits
308 //@{
309 #if defined(__PIC24FJ64GA002__) || defined(__DOXYGEN__)
310 
311 /** Register CONFIG1
312  ** \code
313  ** JTAG:
314  ** -->JTAGEN_OFF Disabled
315  ** JTAGEN_ON Enabled
316  **
317  ** Code Protect:
318  ** GCP_ON Enabled
319  ** -->GCP_OFF Disabled
320  **
321  ** Write Protect:
322  ** GWRP_ON Enabled
323  ** -->GWRP_OFF Disabled
324  **
325  ** Background Debugger:
326  ** BKBUG_ON Enabled
327  ** -->BKBUG_OFF Disabled
328  **
329  ** Clip-on Emulation mode:
330  ** COE_ON Enabled
331  ** -->COE_OFF Disabled
332  **
333  ** ICD pins select:
334  ** ICS_PGx3 EMUC/EMUD share PGC3/PGD3
335  ** ICS_PGx2 EMUC/EMUD share PGC2/PGD2
336  ** -->ICS_PGx1 EMUC/EMUD share PGC1/PGD1
337  **
338  ** Watchdog Timer:
339  ** -->FWDTEN_OFF Disabled
340  ** FWDTEN_ON Enabled
341  **
342  ** Windowed WDT:
343  ** WINDIS_ON Enabled
344  ** -->WINDIS_OFF Disabled
345  **
346  ** Watchdog prescaler:
347  ** FWPSA_PR32 1:32
348  ** -->FWPSA_PR128 1:128
349  **
350  ** Watchdog postscale:
351  ** WDTPS_PS1 1:1
352  ** WDTPS_PS2 1:2
353  ** WDTPS_PS4 1:4
354  ** WDTPS_PS8 1:8
355  ** WDTPS_PS16 1:16
356  ** WDTPS_PS32 1:32
357  ** WDTPS_PS64 1:64
358  ** WDTPS_PS128 1:128
359  ** WDTPS_PS256 1:256
360  ** -->WDTPS_PS512 1:512
361  ** WDTPS_PS1024 1:1,024
362  ** WDTPS_PS2048 1:2,048
363  ** WDTPS_PS4096 1:4,096
364  ** WDTPS_PS8192 1:8,192
365  ** WDTPS_PS16384 1:16,384
366  ** WDTPS_PS32768 1:32,768
367  ** 128*512 = 65536 ~ 0.5 Hz ~ 2 secs (WDT is ~ 31 KHz)
368  \endcode
369  */
370 _CONFIG1(JTAGEN_OFF & GCP_OFF & GWRP_OFF & BKBUG_OFF & COE_OFF & ICS_PGx1 & FWDTEN_OFF & WINDIS_OFF & FWPSA_PR128 & WDTPS_PS512);
371 
372 
373 /** Register CONFIG2
374  ** \code
375  ** Two Speed Start-up:
376  ** -->IESO_OFF Disabled
377  ** IESO_ON Enabled
378  **
379  ** Secondary Oscillator:
380  ** SOSCSEL_LPSOSC Low Power Secondary Oscillator
381  ** SOSCSEL_SOSC Default Secondary Oscillator
382  **
383  ** Voltage Regulator Standby-mode Wake-up Timer:
384  ** WUTSEL_FST Fast Wake-up timer selected
385  ** WUTSEL_LEG Legacy Wake-up timer selected
386  **
387  ** Oscillator Selection:
388  ** -->FNOSC_FRC Fast RC oscillator
389  ** FNOSC_FRCPLL Fast RC oscillator w/ divide and PLL
390  ** FNOSC_PRI Primary oscillator (XT, HS, EC)
391  ** FNOSC_PRIPLL Primary oscillator (XT, HS, EC) w/ PLL
392  ** FNOSC_SOSC Secondary oscillator
393  ** FNOSC_LPRC Low power RC oscillator
394  ** FNOSC_FRCDIV Fast RC oscillator with divide
395  **
396  ** Clock switching and clock monitor:
397  ** FCKSM_CSECME Both enabled
398  ** -->FCKSM_CSECMD Only clock switching enabled
399  ** FCKSM_CSDCMD Both disabled
400  **
401  ** OSCO/RC15 function:
402  ** -->OSCIOFNC_ON RC15
403  ** OSCIOFNC_OFF OSCO or Fosc/2
404  **
405  ** RP Register Protection:
406  ** -->IOL1WAY_OFF Unlimited Writes To RP Registers
407  ** IOL1WAY_ON Write RP Registers Once
408  **
409  ** I2C1 pins Select:
410  ** I2C1SEL_SEC Use Secondary I2C1 pins
411  ** -->I2C1SEL_PRI Use Primary I2C1 pins
412  **
413  ** Oscillator Selection:
414  ** Taken from POSCMD_SEL
415  **
416 \endcode
417 */
418 _CONFIG2(IESO_OFF & FNOSC_FRC & FCKSM_CSECMD & IOL1WAY_OFF & OSCPIN_CONFIG );
419 
420 
421 
422 ///\cond doxygen_ignore
423 #define CONFIG_BITS_DEFINED
424 ///\endcond
425 //@}
426 #endif // #ifdef PIC24F processors
427 
428 #if defined(EXPLORER16_100P) && defined(__PIC24FJ128GA010__)
429 _CONFIG1(JTAGEN_OFF & GCP_OFF & GWRP_OFF & BKBUG_OFF & COE_OFF & ICS_PGx1 & FWDTEN_OFF & WINDIS_OFF & FWPSA_PR128 & WDTPS_PS512);
430 _CONFIG2(IESO_OFF & FNOSC_FRC & FCKSM_CSECMD & OSCPIN_CONFIG);
431 #define CONFIG_BITS_DEFINED
432 #endif
433 
434 #if defined(__PIC24FJ64GB002__) ||(__PIC24FJ64GB004__)
435 _CONFIG1(JTAGEN_OFF & GCP_OFF & GWRP_OFF & ICS_PGx1 & FWDTEN_OFF & WINDIS_OFF & FWPSA_PR128 & WDTPS_PS512);
436 _CONFIG2(IESO_OFF & FNOSC_FRC & FCKSM_CSECMD & IOL1WAY_OFF & PLL96MHZ_OFF & PLLDIV_DIV2 & OSCPIN_CONFIG );
437 _CONFIG4(DSWDTPS_DSWDTPSF & DSWDTEN_OFF & DSBOREN_OFF)
438 #define CONFIG_BITS_DEFINED
439 ///\endcond
440 #endif
441 
442 // Default config bits, use these if a processor is not defined.
443 #ifndef CONFIG_BITS_DEFINED
444 # ifdef __PIC24H__
445 _FBS(BWRP_WRPROTECT_OFF);
446 _FGS(GSS_OFF & GCP_OFF & GWRP_OFF);
447 
448 # ifdef RSS_NO_RAM
449 _FSS(RSS_NO_RAM & SSS_NO_FLASH & SWRP_WRPROTECT_OFF);
450 # endif
451 
452 _FOSC(FCKSM_CSECMD & IOL1WAY_OFF & OSCPIN_CONFIG);
453 
454 _FOSCSEL(FNOSC_FRC & IESO_OFF);
455 _FWDT(FWDTEN_OFF & WINDIS_OFF & WDTPRE_PR128 & WDTPOST_PS512);
456 _FPOR(FPWRT_PWR16);
457 _FICD(JTAGEN_OFF & ICS_PGD1);
458 
459 # warning "Using default config bit settings for the PIC24H family."
460 # warning "Edit this file to define bits for your processor!"
461 ///\cond doxygen_ignore
462 # define CONFIG_BITS_DEFINED
463 ///\endcond
464 # endif
465 
466 # ifdef __PIC24F__
467 
468 # ifndef BKBUG_OFF
469 # define BKBUG_OFF 0xFFFF
470 # endif
471 # ifndef COE_OFF
472 # define COE_OFF 0xFFFF
473 # endif
474 
475 _CONFIG1(JTAGEN_OFF & GCP_OFF & GWRP_OFF & BKBUG_OFF & COE_OFF & ICS_PGx1 & FWDTEN_OFF & WINDIS_OFF & FWPSA_PR128 & WDTPS_PS512);
476 _CONFIG2(IESO_OFF & FNOSC_FRC & FCKSM_CSECMD & IOL1WAY_OFF & OSCPIN_CONFIG);
477 
478 
479 # warning "Using default config bit settings for the PIC24F family."
480 # warning "Edit this file to define bits for your processor!"
481 ///\cond doxygen_ignore
482 # define CONFIG_BITS_DEFINED
483 ///\endcond
484 # endif
485 
486 
487 
488 /* The PIC24FK is a subfamily of the PIC24F -- functionality like the PIC24F, but config bits like the PIC24H */
489 # ifdef __PIC24FK__
490 _FBS(BSS_OFF & BWRP_OFF);
491 _FGS(GWRP_OFF);
492 
493 # if (POSC_FREQ < 100000L)
494 _FOSC(FCKSM_CSECMD & OSCPIN_CONFIG & POSCFREQ_LS);
495 # elif (POSC_FREQ > 8000000L)
496 _FOSC(FCKSM_CSECMD & OSCPIN_CONFIG & POSCFREQ_HS);
497 # else
498 _FOSC(FCKSM_CSECMD & OSCPIN_CONFIG & POSCFREQ_MS);
499 # endif
500 
501 
502 _FOSCSEL(FNOSC_FRC & IESO_OFF);
503 _FWDT(FWDTEN_OFF & WINDIS_OFF & FWPSA_PR128 & WDTPS_PS512);
504 _FPOR(PWRTEN_ON & MCLRE_ON & I2C1SEL_PRI);
505 _FICD(ICS_PGx1);
506 
507 //new config word for deep sleep operation, set these for your needs
508 _FDS(DSWDTEN_OFF & DSBOREN_OFF & DSWDTOSC_SOSC);
509 
510 # warning "Using default config bit settings for the PIC24FK family."
511 # warning "Edit this file to define bits for your processor!"
512 ///\cond doxygen_ignore
513 # define CONFIG_BITS_DEFINED
514 ///\endcond
515 # endif
516 
517 
518 # ifdef __dsPIC33F__
519 _FBS(BWRP_WRPROTECT_OFF);
520 _FGS(GSS_OFF & GCP_OFF & GWRP_OFF);
521 _FOSCSEL(FNOSC_FRC & IESO_OFF);
522 # ifdef RSS_NO_RAM
523 _FSS(RSS_NO_RAM & SSS_NO_FLASH & SWRP_WRPROTECT_OFF);
524 # endif
525 
526 _FOSC(FCKSM_CSECMD & IOL1WAY_OFF & OSCPIN_CONFIG);
527 
528 _FWDT(FWDTEN_OFF & WINDIS_OFF & WDTPRE_PR128 & WDTPOST_PS512);
529 _FPOR(FPWRT_PWR16);
530 _FICD(JTAGEN_OFF & ICS_PGD1 & 0xFFEF);
531 # warning "Using default config bit settings for the dsPIC33F family."
532 # warning "Edit this file to define bits for your processor!"
533 ///\cond doxygen_ignore
534 # define CONFIG_BITS_DEFINED
535 ///\endcond
536 # endif
537 
538 # ifdef __PIC24E__
539 # ifdef GCP_OFF
540 _FGS( GCP_OFF & GWRP_OFF);
541 # else
542 _FGS(0xFFFF);
543 # endif
544 //28 pin devices only have ALT2IC1 pins!!?
545 _FPOR(ALTI2C1_ON & 0xFFFF);
546 
547 _FOSC(FCKSM_CSECMD & IOL1WAY_OFF & OSCPIN_CONFIG);
548 _FOSCSEL(FNOSC_FRC & IESO_OFF);
549 _FWDT(FWDTEN_OFF & WINDIS_OFF & WDTPRE_PR128 & WDTPOST_PS512);
550 _FICD(JTAGEN_OFF & ICS_PGD1 & 0xFFEF);
551 
552 # warning "Using default config bit settings for the PIC24E family."
553 # warning "Edit this file to define bits for your processor!"
554 ///\cond doxygen_ignore
555 # define CONFIG_BITS_DEFINED
556 ///\endcond
557 # endif
558 
559 
560 
561 # ifdef __dsPIC33E__
562 /***********************************************************************************
563 *** The dsPIC33ExxGP5xx and dsPIC33ExxGP8xx devices we use have slightly different
564 *** config bits defined. So we will look for our device and setup config bits
565 *** accordingly. As other devices are added, hopefull they won't differ from these
566 *** two cases....
567 *** .. until Microchip makes another small, subtle change in the datasheets (UGH!)
568 ***********************************************************************************/
569 #if defined(__dsPIC33EP128GP502__) || (__dsPIC33EP128GP504__)
570 // DSPIC33EP128GP502 Configuration Bit Settings
571 // FICD
572 # pragma config ICS = PGD1 // ICD Communication Channel Select bits (Communicate on PGEC1 and PGED1)
573 # pragma config JTAGEN = OFF // JTAG Enable bit (JTAG is disabled)
574 // FPOR
575 # pragma config ALTI2C1 = ON // Alternate I2C1 pins (I2C1 mapped to ASDA1/ASCL1 pins)
576 # pragma config ALTI2C2 = OFF // Alternate I2C2 pins (I2C2 mapped to SDA2/SCL2 pins)
577 # pragma config WDTWIN = WIN25 // Watchdog Window Select bits (WDT Window is 25% of WDT period)
578 // FWDT
579 # pragma config WDTPOST = PS512 // Watchdog Timer Postscaler bits (1:512)
580 # pragma config WDTPRE = PR128 // Watchdog Timer Prescaler bit (1:128)
581 # pragma config PLLKEN = ON // PLL Lock Enable bit (Clock switch to PLL source will wait until the PLL lock signal is valid.)
582 # pragma config WINDIS = OFF // Watchdog Timer Window Enable bit (Watchdog Timer in Non-Window mode)
583 # pragma config FWDTEN = OFF // Watchdog Timer Enable bit (Watchdog timer enabled/disabled by user software)
584 // FOSC
585 // Use the old-style config here, since #pragmas don't work with #defined
586 // constants.
587 //
588 // IOL1WAY_OFF: Peripheral pin select configuration (Allow multiple reconfigurations)
589 // FCKSM_CSDCMD: Clock Switching Mode bits (Both Clock switching and Fail-safe Clock Monitor are disabled)
590 _FOSC(OSCPIN_CONFIG & FCKSM_CSECMD & IOL1WAY_OFF);
591 
592 // FOSCSEL
593 # pragma config FNOSC = FRC // Oscillator Source Selection (Internal Fast RC (FRC))
594 # pragma config IESO = OFF // Two-speed Oscillator Start-up Enable bit (Start up with user-selected oscillator source)
595 // FGS
596 # pragma config GWRP = OFF // General Segment Write-Protect bit (General Segment may be written)
597 # pragma config GCP = OFF // General Segment Code-Protect bit (General Segment Code protect is Disabled)
598 ///\cond doxygen_ignore
599 # define CONFIG_BITS_DEFINED
600 ///\endcond
601 #endif // #ifdefined (__dsPIC33EP128GP502__) || (__dsPIC33EP128GP504__)
602 
603 #if defined(__dsPIC33EP512GP806__)
604 // DSPIC33EP512GP806 Configuration Bit Settings
605 // FICD
606 #pragma config ICS = PGD1 // ICD Communication Channel Select bits (Communicate on PGEC1 and PGED1)
607 #pragma config JTAGEN = OFF // JTAG Enable bit (JTAG is disabled)
608 
609 // FPOR
610 #pragma config ALTI2C1 = ON // Alternate I2C1 pins (I2C1 mapped to ASDA1/ASCL1 pins)
611 #pragma config BOREN = ON // BROWN-OUT RESET DETECTION MUST BE ENABLED (per datasheet DS70616G p.479)
612 #pragma config FPWRT = PWR1 // POWER ON RESET TIMER DISABLED?
613 
614 
615 // FWDT
616 #pragma config WDTPOST = PS512 // Watchdog Timer Postscaler bits (1:512)
617 #pragma config WDTPRE = PR128 // Watchdog Timer Prescaler bit (1:128)
618 #pragma config PLLKEN = ON // PLL Lock Enable bit (Clock switch to PLL source will wait until the PLL lock signal is valid.)
619 #pragma config WINDIS = OFF // Watchdog Timer Window Enable bit (Watchdog Timer in Non-Window mode)
620 #pragma config FWDTEN = OFF // Watchdog Timer Enable bit (Watchdog timer enabled/disabled by user software)
621 
622 // FOSC
623 #if POSCMD_SEL == POSCMD_EC
624 #pragma config POSCMD = EC // Primary Oscillator Mode Select bits (EC Crystal Oscillator Mode)
625 #pragma config OSCIOFNC = OFF // OSC2 Pin Function bit (OSC2 is clock output)
626 #elif POSCMD_SEL == POSCMD_XT
627 #pragma config POSCMD = XT // Primary Oscillator Mode Select bits (XT Crystal Oscillator Mode)
628 #pragma config OSCIOFNC = OFF // OSC2 Pin Function bit (OSC2 is clock output)
629 #elif POSCMD_SEL == POSCMD_HS
630 #pragma config POSCMD = HS // Primary Oscillator Mode Select bits (HS Crystal Oscillator Mode)
631 #pragma config OSCIOFNC = OFF // OSC2 Pin Function bit (OSC2 is clock output)
632 #elif POSCMD_SEL == POSCMD_NONE
633 #pragma config POSCMD = NONE // Primary Oscillator Mode Select bits (Primary Oscillator disabled)
634 #pragma config OSCIOFNC = ON // OSC2 Pin Function bit (OSC2 is general purpose digital I/O pin)
635 #else
636 # error "Unknown primary oscillator selection."
637 #endif
638 
639 #pragma config IOL1WAY = OFF // Peripheral pin select configuration (Allow multiple reconfigurations)
640 #pragma config FCKSM = CSECMD // Clock Switching Mode bits (Clock switching is enabled,Fail-safe Clock Monitor is disabled)
641 
642 // FOSCSEL
643 #pragma config FNOSC = FRC // Oscillator Source Selection (Internal Fast RC (FRC))
644 #pragma config IESO = OFF // Two-speed Oscillator Start-up Enable bit (Start up with user-selected oscillator source)
645 
646 // FGS
647 #pragma config GWRP = OFF // General Segment Write-Protect bit (General Segment may be written)
648 #pragma config GSS = OFF // General Segment Code-Protect bit (General Segment Code protect is Disabled)
649 #pragma config GSSK = OFF // General Segment KEY bit (General Segment protect is Disabled)
650 
651 #define CONFIG_BITS_DEFINED
652 ///\endcond
653 #endif // #ifdefined (__dsPIC33EP512GP806__)
654 
655 #endif // #ifdef __dsPIC33E__
656 
657 #endif // #ifndef CONFIG_BITS_DEFINED
658 
659 //
660 // If the chip currently-in-use has not be detected, the config bits
661 // have not be setup properly, so issue an error.
662 // Other chips can be added to this file as we use/need them.
663 //
664 #ifndef CONFIG_BITS_DEFINED
665 # error "Edit common/pic24_configbits.c to add config bits for your processor!"
666 #endif