71 # define IOL1WAY_OFF 0xFFFF
76 # define OSCIOFNC_OFF 0xFFFF
85 # define OSCPIN_CONFIG (OSCIOFNC_OFF & POSCMD_XT)
88 # if POSCMD_SEL == POSCMD_NONE
90 # define OSCPIN_CONFIG (OSCIOFNC_ON & POSCMD_NONE)
94 # define OSCPIN_CONFIG (OSCIOFNC_OFF & POSCMD_SEL)
102 #if defined(__PIC24HJ12GP202__) || \
103 defined(__PIC24HJ12GP201__) || \
104 defined(__PIC24HJ32GP202__) || \
105 defined(__PIC24HJ32GP202__) || \
106 defined(__PIC24HJ16GP304__) || \
107 defined(__DOXYGEN__) // NOTE: DOXYGEN only used for documentation generation
134 _FBS(BWRP_WRPROTECT_OFF);
159 _FGS(GSS_OFF & GCP_OFF & GWRP_OFF);
207 _FOSC(FCKSM_CSECMD & IOL1WAY_OFF & OSCPIN_CONFIG );
245 _FWDT(FWDTEN_OFF & WINDIS_OFF & WDTPRE_PR128 & WDTPOST_PS512);
265 _FPOR(FPWRT_PWR16 & ALTI2C_OFF);
285 _FICD(JTAGEN_OFF & ICS_PGD1);
288 #define CONFIG_BITS_DEFINED
291 #endif // #ifdef (lots of PIC24H devices)
295 #if defined(EXPLORER16_100P) && defined(__PIC24HJ256GP610__)
296 _FBS(BWRP_WRPROTECT_OFF);
297 _FGS(GSS_OFF & GCP_OFF & GWRP_OFF);
299 _FOSC(FCKSM_CSECMD & OSCPIN_CONFIG );
300 _FWDT(FWDTEN_OFF & WINDIS_OFF & WDTPRE_PR128 & WDTPOST_PS512);
302 _FICD(JTAGEN_OFF & ICS_PGD1);
303 #define CONFIG_BITS_DEFINED
309 #if defined(__PIC24FJ64GA002__) || defined(__DOXYGEN__)
370 _CONFIG1(JTAGEN_OFF & GCP_OFF & GWRP_OFF & BKBUG_OFF & COE_OFF & ICS_PGx1 & FWDTEN_OFF & WINDIS_OFF & FWPSA_PR128 & WDTPS_PS512);
418 _CONFIG2(IESO_OFF & FNOSC_FRC & FCKSM_CSECMD & IOL1WAY_OFF & OSCPIN_CONFIG );
423 #define CONFIG_BITS_DEFINED
426 #endif // #ifdef PIC24F processors
428 #if defined(EXPLORER16_100P) && defined(__PIC24FJ128GA010__)
429 _CONFIG1(JTAGEN_OFF & GCP_OFF & GWRP_OFF & BKBUG_OFF & COE_OFF & ICS_PGx1 & FWDTEN_OFF & WINDIS_OFF & FWPSA_PR128 & WDTPS_PS512);
430 _CONFIG2(IESO_OFF & FNOSC_FRC & FCKSM_CSECMD & OSCPIN_CONFIG);
431 #define CONFIG_BITS_DEFINED
434 #if defined(__PIC24FJ64GB002__) ||(__PIC24FJ64GB004__)
435 _CONFIG1(JTAGEN_OFF & GCP_OFF & GWRP_OFF & ICS_PGx1 & FWDTEN_OFF & WINDIS_OFF & FWPSA_PR128 & WDTPS_PS512);
436 _CONFIG2(IESO_OFF & FNOSC_FRC & FCKSM_CSECMD & IOL1WAY_OFF & PLL96MHZ_OFF & PLLDIV_DIV2 & OSCPIN_CONFIG );
437 _CONFIG4(DSWDTPS_DSWDTPSF & DSWDTEN_OFF & DSBOREN_OFF)
438 #define CONFIG_BITS_DEFINED
443 #ifndef CONFIG_BITS_DEFINED
445 _FBS(BWRP_WRPROTECT_OFF);
446 _FGS(GSS_OFF & GCP_OFF & GWRP_OFF);
449 _FSS(RSS_NO_RAM & SSS_NO_FLASH & SWRP_WRPROTECT_OFF);
452 _FOSC(FCKSM_CSECMD & IOL1WAY_OFF & OSCPIN_CONFIG);
455 _FWDT(FWDTEN_OFF & WINDIS_OFF & WDTPRE_PR128 & WDTPOST_PS512);
457 _FICD(JTAGEN_OFF & ICS_PGD1);
459 # warning "Using default config bit settings for the PIC24H family."
460 # warning "Edit this file to define bits for your processor!"
462 # define CONFIG_BITS_DEFINED
469 # define BKBUG_OFF 0xFFFF
472 # define COE_OFF 0xFFFF
475 _CONFIG1(JTAGEN_OFF & GCP_OFF & GWRP_OFF & BKBUG_OFF & COE_OFF & ICS_PGx1 & FWDTEN_OFF & WINDIS_OFF & FWPSA_PR128 & WDTPS_PS512);
476 _CONFIG2(IESO_OFF & FNOSC_FRC & FCKSM_CSECMD & IOL1WAY_OFF & OSCPIN_CONFIG);
479 # warning "Using default config bit settings for the PIC24F family."
480 # warning "Edit this file to define bits for your processor!"
482 # define CONFIG_BITS_DEFINED
490 _FBS(BSS_OFF & BWRP_OFF);
493 # if (POSC_FREQ < 100000L)
494 _FOSC(FCKSM_CSECMD & OSCPIN_CONFIG & POSCFREQ_LS);
495 # elif (POSC_FREQ > 8000000L)
496 _FOSC(FCKSM_CSECMD & OSCPIN_CONFIG & POSCFREQ_HS);
498 _FOSC(FCKSM_CSECMD & OSCPIN_CONFIG & POSCFREQ_MS);
503 _FWDT(FWDTEN_OFF & WINDIS_OFF & FWPSA_PR128 & WDTPS_PS512);
504 _FPOR(PWRTEN_ON & MCLRE_ON & I2C1SEL_PRI);
508 _FDS(DSWDTEN_OFF & DSBOREN_OFF & DSWDTOSC_SOSC);
510 # warning "Using default config bit settings for the PIC24FK family."
511 # warning "Edit this file to define bits for your processor!"
513 # define CONFIG_BITS_DEFINED
519 _FBS(BWRP_WRPROTECT_OFF);
520 _FGS(GSS_OFF & GCP_OFF & GWRP_OFF);
523 _FSS(RSS_NO_RAM & SSS_NO_FLASH & SWRP_WRPROTECT_OFF);
526 _FOSC(FCKSM_CSECMD & IOL1WAY_OFF & OSCPIN_CONFIG);
528 _FWDT(FWDTEN_OFF & WINDIS_OFF & WDTPRE_PR128 & WDTPOST_PS512);
530 _FICD(JTAGEN_OFF & ICS_PGD1 & 0xFFEF);
531 # warning "Using default config bit settings for the dsPIC33F family."
532 # warning "Edit this file to define bits for your processor!"
534 # define CONFIG_BITS_DEFINED
540 _FGS( GCP_OFF & GWRP_OFF);
545 _FPOR(ALTI2C1_ON & 0xFFFF);
547 _FOSC(FCKSM_CSECMD & IOL1WAY_OFF & OSCPIN_CONFIG);
549 _FWDT(FWDTEN_OFF & WINDIS_OFF & WDTPRE_PR128 & WDTPOST_PS512);
550 _FICD(JTAGEN_OFF & ICS_PGD1 & 0xFFEF);
552 # warning "Using default config bit settings for the PIC24E family."
553 # warning "Edit this file to define bits for your processor!"
555 # define CONFIG_BITS_DEFINED
569 #if defined(__dsPIC33EP128GP502__) || (__dsPIC33EP128GP504__)
572 # pragma config ICS = PGD1 // ICD Communication Channel Select bits (Communicate on PGEC1 and PGED1)
573 # pragma config JTAGEN = OFF // JTAG Enable bit (JTAG is disabled)
575 # pragma config ALTI2C1 = ON // Alternate I2C1 pins (I2C1 mapped to ASDA1/ASCL1 pins)
576 # pragma config ALTI2C2 = OFF // Alternate I2C2 pins (I2C2 mapped to SDA2/SCL2 pins)
577 # pragma config WDTWIN = WIN25 // Watchdog Window Select bits (WDT Window is 25% of WDT period)
579 # pragma config WDTPOST = PS512 // Watchdog Timer Postscaler bits (1:512)
580 # pragma config WDTPRE = PR128 // Watchdog Timer Prescaler bit (1:128)
581 # pragma config PLLKEN = ON // PLL Lock Enable bit (Clock switch to PLL source will wait until the PLL lock signal is valid.)
582 # pragma config WINDIS = OFF // Watchdog Timer Window Enable bit (Watchdog Timer in Non-Window mode)
583 # pragma config FWDTEN = OFF // Watchdog Timer Enable bit (Watchdog timer enabled/disabled by user software)
590 _FOSC(OSCPIN_CONFIG & FCKSM_CSECMD & IOL1WAY_OFF);
593 # pragma config FNOSC = FRC // Oscillator Source Selection (Internal Fast RC (FRC))
594 # pragma config IESO = OFF // Two-speed Oscillator Start-up Enable bit (Start up with user-selected oscillator source)
596 # pragma config GWRP = OFF // General Segment Write-Protect bit (General Segment may be written)
597 # pragma config GCP = OFF // General Segment Code-Protect bit (General Segment Code protect is Disabled)
599 # define CONFIG_BITS_DEFINED
601 #endif // #ifdefined (__dsPIC33EP128GP502__) || (__dsPIC33EP128GP504__)
603 #if defined(__dsPIC33EP512GP806__)
606 #pragma config ICS = PGD1 // ICD Communication Channel Select bits (Communicate on PGEC1 and PGED1)
607 #pragma config JTAGEN = OFF // JTAG Enable bit (JTAG is disabled)
610 #pragma config ALTI2C1 = ON // Alternate I2C1 pins (I2C1 mapped to ASDA1/ASCL1 pins)
611 #pragma config BOREN = ON // BROWN-OUT RESET DETECTION MUST BE ENABLED (per datasheet DS70616G p.479)
612 #pragma config FPWRT = PWR1 // POWER ON RESET TIMER DISABLED?
616 #pragma config WDTPOST = PS512 // Watchdog Timer Postscaler bits (1:512)
617 #pragma config WDTPRE = PR128 // Watchdog Timer Prescaler bit (1:128)
618 #pragma config PLLKEN = ON // PLL Lock Enable bit (Clock switch to PLL source will wait until the PLL lock signal is valid.)
619 #pragma config WINDIS = OFF // Watchdog Timer Window Enable bit (Watchdog Timer in Non-Window mode)
620 #pragma config FWDTEN = OFF // Watchdog Timer Enable bit (Watchdog timer enabled/disabled by user software)
623 #if POSCMD_SEL == POSCMD_EC
624 #pragma config POSCMD = EC // Primary Oscillator Mode Select bits (EC Crystal Oscillator Mode)
625 #pragma config OSCIOFNC = OFF // OSC2 Pin Function bit (OSC2 is clock output)
626 #elif POSCMD_SEL == POSCMD_XT
627 #pragma config POSCMD = XT // Primary Oscillator Mode Select bits (XT Crystal Oscillator Mode)
628 #pragma config OSCIOFNC = OFF // OSC2 Pin Function bit (OSC2 is clock output)
629 #elif POSCMD_SEL == POSCMD_HS
630 #pragma config POSCMD = HS // Primary Oscillator Mode Select bits (HS Crystal Oscillator Mode)
631 #pragma config OSCIOFNC = OFF // OSC2 Pin Function bit (OSC2 is clock output)
632 #elif POSCMD_SEL == POSCMD_NONE
633 #pragma config POSCMD = NONE // Primary Oscillator Mode Select bits (Primary Oscillator disabled)
634 #pragma config OSCIOFNC = ON // OSC2 Pin Function bit (OSC2 is general purpose digital I/O pin)
636 # error "Unknown primary oscillator selection."
639 #pragma config IOL1WAY = OFF // Peripheral pin select configuration (Allow multiple reconfigurations)
640 #pragma config FCKSM = CSECMD // Clock Switching Mode bits (Clock switching is enabled,Fail-safe Clock Monitor is disabled)
643 #pragma config FNOSC = FRC // Oscillator Source Selection (Internal Fast RC (FRC))
644 #pragma config IESO = OFF // Two-speed Oscillator Start-up Enable bit (Start up with user-selected oscillator source)
647 #pragma config GWRP = OFF // General Segment Write-Protect bit (General Segment may be written)
648 #pragma config GSS = OFF // General Segment Code-Protect bit (General Segment Code protect is Disabled)
649 #pragma config GSSK = OFF // General Segment KEY bit (General Segment protect is Disabled)
651 #define CONFIG_BITS_DEFINED
653 #endif // #ifdefined (__dsPIC33EP512GP806__)
655 #endif // #ifdef __dsPIC33E__
657 #endif // #ifndef CONFIG_BITS_DEFINED
664 #ifndef CONFIG_BITS_DEFINED
665 # error "Edit common/pic24_configbits.c to add config bits for your processor!"