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31 #define COMP_CVRCON_VAL 0x0000
32 #define COMP_CMCON_VAL 0x0000
34 #define CMP_IDLE_STOP 0x8000
35 #define CMP_IDLE_CON 0x0000
36 #define CMP_IDLE_MASK (~CMP_IDLE_STOP)
38 #define CMP2_CHANGE_STATE 0x2000
39 #define CMP2_NO_CHANGE 0x0000
40 #define CMP2_STATE_MASK (~CMP2_CHANGE_STATE )
42 #define CMP1_CHANGE_STATE 0x1000
43 #define CMP1_NO_CHANGE 0x0000
44 #define CMP1_ENBL_DSBL_MASK (~CMP1_CHANGE_STATE )
46 #define CMP2_ENABLE 0x0800
47 #define CMP2_DISABLE 0x0000
48 #define CMP2_ENBL_DSBL_MASK (~CMP2_ENABLE)
50 #define CMP1_ENABLE 0x0400
51 #define CMP1_DISABLE 0x0000
52 #define CMP1_STATE_MASK (~CMP1_ENABLE)
54 #define CMP2_OUTPUT_ENABLE 0x0200
55 #define CMP2_OUTPUT_DISABLE 0x0000
56 #define CMP2_OUTPUT_MASK (~CMP2_OUTPUT_ENABLE)
58 #define CMP1_OUTPUT_ENABLE 0x0100
59 #define CMP1_OUTPUT_DISABLE 0x0000
60 #define CMP1_OUTPUT_MASK (~CMP1_OUTPUT_ENABLE)
62 #define CMP2_INV_OUTPUT 0x0020
63 #define CMP2_NORMAL_OUTPUT 0x0000
64 #define CMP2_INV_OUTPUT_MASK (~CMP2_INV_OUTPUT)
66 #define CMP1_INV_OUTPUT 0x0010
67 #define CMP1_NORMAL_OUTPUT 0x0000
68 #define CMP1_INV_OUTPUT_MASK (~CMP1_INV_OUTPUT)
70 #define CMP2_NEG_IP_VIN_POS 0x0008
71 #define CMP2_NEG_IP_VIN_NEG 0x0000
72 #define CMP2_NEG_IP_MASK (~CMP2_NEG_IP_VIN_POS)
74 #define CMP2_POS_IP_VIN_POS 0x0004
75 #define CMP2_POS_IP_CV_REF 0x0000
76 #define CMP2_POS_IP_MASK (~CMP2_POS_IP_VIN_POS)
78 #define CMP1_NEG_IP_VIN_POS 0x0002
79 #define CMP1_NEG_IP_VIN_NEG 0x0000
80 #define CMP1_NEG_IP_MASK (~CMP1_NEG_IP_VIN_POS)
82 #define CMP1_POS_IP_VIN_POS 0x0001
83 #define CMP1_POS_IP_CV_REF 0x0000
84 #define CMP1_POS_IP_MASK (~CMP1_POS_IP_VIN_POS)
86 #define CMP_VREF_ENABLE 0x0080
87 #define CMP_VREF_DISABLE 0x0000
88 #define CMP1_VREF_MASK (~CMP_VREF_ENABLE)
90 #define CMP_VREF_OUTPUT_ENABLE 0x0040
91 #define CMP_VREF_OUTPUT_DISABLE 0x0000
92 #define CMP_VREF_OUTPUT_MASK (~CMP_VREF_OUTPUT_ENABLE)
94 #define CMP_VREF_SELECT_24_STEPS 0x0020
95 #define CMP_VREF_SELECT_32_STEPS 0x0000
96 #define CMP_VREF_STEP_SELECT_MASK (~CMP_VREF_SELECT_24_STEPS)
98 #define CMP_VRSRC_VREF_VREF 0x0010
99 #define CMP_VRSRC_AVDD_AVSS 0x0000
100 #define CMP_VRSRC_MASK (~CMP_VRSRC_VREF_VREF)
103 #define CMP_0P0_CVRR_1 0x0020
104 #define CMP_0P04_CVRR_1 0x0021
105 #define CMP_0P08_CVRR_1 0x0022
106 #define CMP_0P12_CVRR_1 0x0023
107 #define CMP_0P16_CVRR_1 0x0024
108 #define CMP_0P20_CVRR_1 0x0025
109 #define CMP_0P25_CVRR_1 0x0026
110 #define CMP_0P29_CVRR_1 0x0027
111 #define CMP_0P33_CVRR_1 0x0028
112 #define CMP_0P37_CVRR_1 0x0029
113 #define CMP_0P41_CVRR_1 0x002A
114 #define CMP_0P45_CVRR_1 0x002B
115 #define CMP_0P50_CVRR_1 0x002C
116 #define CMP_0P54_CVRR_1 0x002D
117 #define CMP_0P58_CVRR_1 0x002E
118 #define CMP_0P62_CVRR_1 0x002F
120 #define CMP_0P25_CVRR_0 0x0000
121 #define CMP_0P28_CVRR_0 0x0001
122 #define CMP_0P31_CVRR_0 0x0002
123 #define CMP_0P34_CVRR_0 0x0003
124 #define CMP_0P37_CVRR_0 0x0004
125 #define CMP_0P40_CVRR_0 0x0005
126 #define CMP_0P43_CVRR_0 0x0006
127 #define CMP_0P46_CVRR_0 0x0007
128 #define CMP_0P50_CVRR_0 0x0008
129 #define CMP_0P53_CVRR_0 0x0009
130 #define CMP_0P56_CVRR_0 0x000A
131 #define CMP_0P59_CVRR_0 0x000B
132 #define CMP_0P62_CVRR_0 0x000C
133 #define CMP_0P65_CVRR_0 0x000D
134 #define CMP_0P68_CVRR_0 0x000E
135 #define CMP_0P71_CVRR_0 0x000F