41 #if (NUM_UART_MODS >= 1)
90 #ifdef UART1_TX_INTERRUPT
94 # ifndef UART1_TX_FIFO_SIZE
95 # define UART1_TX_FIFO_SIZE 32 //choose a size
98 # ifndef UART1_TX_INTERRUPT_PRIORITY
99 # define UART1_TX_INTERRUPT_PRIORITY 1
102 volatile uint8_t au8_txFifo1[UART1_TX_FIFO_SIZE];
103 volatile uint16_t u16_txFifo1Head = 0;
104 volatile uint16_t u16_txFifo1Tail = 0;
113 u16_tmp = u16_txFifo1Head;
115 if (u16_tmp == UART1_TX_FIFO_SIZE) u16_tmp = 0;
116 while (u16_tmp == u16_txFifo1Tail)
119 au8_txFifo1[u16_tmp] = u8_c;
120 u16_txFifo1Head = u16_tmp;
124 void _ISR _U1TXInterrupt (
void) {
125 if (u16_txFifo1Head == u16_txFifo1Tail) {
131 if (u16_txFifo1Tail == UART1_TX_FIFO_SIZE)
135 U1TXREG = au8_txFifo1[u16_txFifo1Tail];
153 #ifdef UART1_RX_INTERRUPT
155 # ifndef UART1_RX_FIFO_SIZE
156 # define UART1_RX_FIFO_SIZE 32 //choose a size
159 # ifndef UART1_RX_INTERRUPT_PRIORITY
160 # define UART1_RX_INTERRUPT_PRIORITY 1
163 volatile uint8_t au8_rxFifo1[UART1_RX_FIFO_SIZE];
164 volatile uint16_t u16_rxFifo1Head = 0;
165 volatile uint16_t u16_rxFifo1Tail = 0;
171 return(u16_rxFifo1Head != u16_rxFifo1Tail);
179 while (u16_rxFifo1Head == u16_rxFifo1Tail)
182 if (u16_rxFifo1Tail == UART1_RX_FIFO_SIZE) u16_rxFifo1Tail=0;
183 return au8_rxFifo1[u16_rxFifo1Tail];
186 void _ISR _U1RXInterrupt (
void) {
193 if (u16_rxFifo1Head == UART1_RX_FIFO_SIZE)
195 if (u16_rxFifo1Head == u16_rxFifo1Tail) {
199 au8_rxFifo1[u16_rxFifo1Head] = u8_c;
227 #endif // # ifndef BOOTLOADER
228 #if !defined(BOOTLOADER) || (DEFAULT_UART == 1)
233 #ifndef DEFAULT_BRGH1
234 # define DEFAULT_BRGH1 DEFAULT_BRGH
237 #if (DEFAULT_BRGH1 != 0) && (DEFAULT_BRGH1 != 1)
238 # error "Invalid value specified for DEFAULT_BRGH1."
256 #if (HARDWARE_PLATFORM == EXPLORER16_100P) || (HARDWARE_PLATFORM == HARDMAPPED_UART)
262 # if (HARDWARE_PLATFORM == DANGEROUS_WEB)
263 # warning Building configUART1() for the Dangerous Web target.
268 # elif (HARDWARE_PLATFORM == STARTER_BOARD_28P)
269 # warning Building configUART1() for the StarterBoard_28P target.
274 # elif (HARDWARE_PLATFORM == DEFAULT_DESIGN) || (HARDWARE_PLATFORM == MICROSTICK2)
279 # elif (HARDWARE_PLATFORM == EMBEDDED_C1)
280 # warning Building configUART1() for the Rev.C1 Embedded Systems target.
285 # elif (HARDWARE_PLATFORM == EMBEDDED_F14)
286 # warning Building configUART1() for the Rev.F14 Embedded Systems target.
292 # error "Unknown hardware platform."
295 # warning "UART1 pin mappings not defined. See comments below for more info."
344 #
if (defined(__dsPIC33E__) || defined(__PIC24E__))
361 ASSERT(u32_baudRate >= 1000L);
370 while (U1STAbits.PERR || U1STAbits.FERR) {
375 #ifdef UART1_RX_INTERRUPT
377 _U1RXIP = UART1_RX_INTERRUPT_PRIORITY;
380 #ifdef UART1_TX_INTERRUPT
382 _U1TXIP = UART1_TX_INTERRUPT_PRIORITY;
388 #endif // #if !defined(BOOTLOADER) || (DEFAULT_UART == 1)
390 #endif // #if (NUM_UARTS >= 1)
431 #if (NUM_UART_MODS >= 2)
460 void checkRxErrorUART2(
void) {
463 if (U2STAbits.PERR) {
467 if (U2STAbits.FERR) {
471 if (U2STAbits.OERR) {
480 #ifdef UART2_TX_INTERRUPT
484 # ifndef UART2_TX_FIFO_SIZE
485 # define UART2_TX_FIFO_SIZE 32 //choose a size
488 # ifndef UART2_TX_INTERRUPT_PRIORITY
489 # define UART2_TX_INTERRUPT_PRIORITY 1
492 volatile uint8_t au8_txFifo2[UART2_TX_FIFO_SIZE];
493 volatile uint16_t u16_txFifo2Head = 0;
494 volatile uint16_t u16_txFifo2Tail = 0;
503 u16_tmp = u16_txFifo2Head;
505 if (u16_tmp == UART2_TX_FIFO_SIZE) u16_tmp = 0;
506 while (u16_tmp == u16_txFifo2Tail)
509 au8_txFifo2[u16_tmp] = u8_c;
510 u16_txFifo2Head = u16_tmp;
514 void _ISR _U2TXInterrupt (
void) {
515 if (u16_txFifo2Head == u16_txFifo2Tail) {
521 if (u16_txFifo2Tail == UART2_TX_FIFO_SIZE)
525 U2TXREG = au8_txFifo2[u16_txFifo2Tail];
537 while (IS_TRANSMIT_BUFFER_FULL_UART2())
543 #ifdef UART2_RX_INTERRUPT
545 # ifndef UART2_RX_FIFO_SIZE
546 # define UART2_RX_FIFO_SIZE 32 //choose a size
549 # ifndef UART2_RX_INTERRUPT_PRIORITY
550 # define UART2_RX_INTERRUPT_PRIORITY 1
553 volatile uint8_t au8_rxFifo2[UART2_RX_FIFO_SIZE];
554 volatile uint16_t u16_rxFifo2Head = 0;
555 volatile uint16_t u16_rxFifo2Tail = 0;
561 return(u16_rxFifo2Head != u16_rxFifo2Tail);
569 while (u16_rxFifo2Head == u16_rxFifo2Tail)
572 if (u16_rxFifo2Tail == UART2_RX_FIFO_SIZE) u16_rxFifo2Tail=0;
573 return au8_rxFifo2[u16_rxFifo2Tail];
576 void _ISR _U2RXInterrupt (
void) {
583 if (u16_rxFifo2Head == UART2_RX_FIFO_SIZE)
585 if (u16_rxFifo2Head == u16_rxFifo2Tail) {
589 au8_rxFifo2[u16_rxFifo2Head] = u8_c;
597 return(IS_CHAR_READY_UART2());
608 while (!IS_CHAR_READY_UART2())
617 #endif // # ifndef BOOTLOADER
618 #if !defined(BOOTLOADER) || (DEFAULT_UART == 2)
623 #ifndef DEFAULT_BRGH2
624 # define DEFAULT_BRGH2 DEFAULT_BRGH
627 #if (DEFAULT_BRGH2 != 0) && (DEFAULT_BRGH2 != 1)
628 # error "Invalid value specified for DEFAULT_BRGH2."
640 void configUART2(uint32_t u32_baudRate) {
646 #if (HARDWARE_PLATFORM == EXPLORER16_100P) || (HARDWARE_PLATFORM == HARDMAPPED_UART)
652 # if (HARDWARE_PLATFORM == DANGEROUS_WEB)
653 # warning Building configUART2() for the Dangerous Web target.
658 # elif (HARDWARE_PLATFORM == STARTER_BOARD_28P)
659 # warning Building configUART2() for the StarterBoard_28P target.
664 # elif (HARDWARE_PLATFORM == DEFAULT_DESIGN) || (HARDWARE_PLATFORM == MICROSTICK2)
669 # elif (HARDWARE_PLATFORM == EMBEDDED_C1)
670 # warning Building configUART2() for the Rev.C1 Embedded Systems target.
675 # elif (HARDWARE_PLATFORM == EMBEDDED_F14)
676 # warning Building configUART2() for the Rev.F14 Embedded Systems target.
682 # error "Unknown hardware platform."
685 # warning "UART2 pin mappings not defined. See comments below for more info."
721 (DEFAULT_BRGH2 << 3) |
734 #
if (defined(__dsPIC33E__) || defined(__PIC24E__))
751 ASSERT(u32_baudRate >= 1000L);
760 while (U2STAbits.PERR || U2STAbits.FERR) {
765 #ifdef UART2_RX_INTERRUPT
767 _U2RXIP = UART2_RX_INTERRUPT_PRIORITY;
770 #ifdef UART2_TX_INTERRUPT
772 _U2TXIP = UART2_TX_INTERRUPT_PRIORITY;
778 #endif // #if !defined(BOOTLOADER) || (DEFAULT_UART == 2)
780 #endif // #if (NUM_UARTS >= 2)
821 #if (NUM_UART_MODS >= 3)
850 void checkRxErrorUART3(
void) {
853 if (U3STAbits.PERR) {
857 if (U3STAbits.FERR) {
861 if (U3STAbits.OERR) {
870 #ifdef UART3_TX_INTERRUPT
874 # ifndef UART3_TX_FIFO_SIZE
875 # define UART3_TX_FIFO_SIZE 32 //choose a size
878 # ifndef UART3_TX_INTERRUPT_PRIORITY
879 # define UART3_TX_INTERRUPT_PRIORITY 1
882 volatile uint8_t au8_txFifo3[UART3_TX_FIFO_SIZE];
883 volatile uint16_t u16_txFifo3Head = 0;
884 volatile uint16_t u16_txFifo3Tail = 0;
893 u16_tmp = u16_txFifo3Head;
895 if (u16_tmp == UART3_TX_FIFO_SIZE) u16_tmp = 0;
896 while (u16_tmp == u16_txFifo3Tail)
899 au8_txFifo3[u16_tmp] = u8_c;
900 u16_txFifo3Head = u16_tmp;
904 void _ISR _U3TXInterrupt (
void) {
905 if (u16_txFifo3Head == u16_txFifo3Tail) {
911 if (u16_txFifo3Tail == UART3_TX_FIFO_SIZE)
915 U3TXREG = au8_txFifo3[u16_txFifo3Tail];
927 while (IS_TRANSMIT_BUFFER_FULL_UART3())
933 #ifdef UART3_RX_INTERRUPT
935 # ifndef UART3_RX_FIFO_SIZE
936 # define UART3_RX_FIFO_SIZE 32 //choose a size
939 # ifndef UART3_RX_INTERRUPT_PRIORITY
940 # define UART3_RX_INTERRUPT_PRIORITY 1
943 volatile uint8_t au8_rxFifo3[UART3_RX_FIFO_SIZE];
944 volatile uint16_t u16_rxFifo3Head = 0;
945 volatile uint16_t u16_rxFifo3Tail = 0;
951 return(u16_rxFifo3Head != u16_rxFifo3Tail);
959 while (u16_rxFifo3Head == u16_rxFifo3Tail)
962 if (u16_rxFifo3Tail == UART3_RX_FIFO_SIZE) u16_rxFifo3Tail=0;
963 return au8_rxFifo3[u16_rxFifo3Tail];
966 void _ISR _U3RXInterrupt (
void) {
973 if (u16_rxFifo3Head == UART3_RX_FIFO_SIZE)
975 if (u16_rxFifo3Head == u16_rxFifo3Tail) {
979 au8_rxFifo3[u16_rxFifo3Head] = u8_c;
987 return(IS_CHAR_READY_UART3());
998 while (!IS_CHAR_READY_UART3())
1000 checkRxErrorUART3();
1007 #endif // # ifndef BOOTLOADER
1008 #if !defined(BOOTLOADER) || (DEFAULT_UART == 3)
1013 #ifndef DEFAULT_BRGH3
1014 # define DEFAULT_BRGH3 DEFAULT_BRGH
1017 #if (DEFAULT_BRGH3 != 0) && (DEFAULT_BRGH3 != 1)
1018 # error "Invalid value specified for DEFAULT_BRGH3."
1030 void configUART3(uint32_t u32_baudRate) {
1036 #if (HARDWARE_PLATFORM == EXPLORER16_100P) || (HARDWARE_PLATFORM == HARDMAPPED_UART)
1042 # if (HARDWARE_PLATFORM == DANGEROUS_WEB)
1043 # warning Building configUART3() for the Dangerous Web target.
1048 # elif (HARDWARE_PLATFORM == STARTER_BOARD_28P)
1049 # warning Building configUART3() for the StarterBoard_28P target.
1054 # elif (HARDWARE_PLATFORM == DEFAULT_DESIGN) || (HARDWARE_PLATFORM == MICROSTICK2)
1059 # elif (HARDWARE_PLATFORM == EMBEDDED_C1)
1060 # warning Building configUART3() for the Rev.C1 Embedded Systems target.
1065 # elif (HARDWARE_PLATFORM == EMBEDDED_F14)
1066 # warning Building configUART3() for the Rev.F14 Embedded Systems target.
1072 # error "Unknown hardware platform."
1075 # warning "UART3 pin mappings not defined. See comments below for more info."
1090 U3MODE = (0u << 15);
1111 (DEFAULT_BRGH3 << 3) |
1124 #
if (defined(__dsPIC33E__) || defined(__PIC24E__))
1141 ASSERT(u32_baudRate >= 1000L);
1150 while (U3STAbits.PERR || U3STAbits.FERR) {
1155 #ifdef UART3_RX_INTERRUPT
1157 _U3RXIP = UART3_RX_INTERRUPT_PRIORITY;
1160 #ifdef UART3_TX_INTERRUPT
1162 _U3TXIP = UART3_TX_INTERRUPT_PRIORITY;
1168 #endif // #if !defined(BOOTLOADER) || (DEFAULT_UART == 3)
1170 #endif // #if (NUM_UARTS >= 3)
1211 #if (NUM_UART_MODS >= 4)
1240 void checkRxErrorUART4(
void) {
1243 if (U4STAbits.PERR) {
1247 if (U4STAbits.FERR) {
1251 if (U4STAbits.OERR) {
1260 #ifdef UART4_TX_INTERRUPT
1264 # ifndef UART4_TX_FIFO_SIZE
1265 # define UART4_TX_FIFO_SIZE 32 //choose a size
1268 # ifndef UART4_TX_INTERRUPT_PRIORITY
1269 # define UART4_TX_INTERRUPT_PRIORITY 1
1272 volatile uint8_t au8_txFifo4[UART4_TX_FIFO_SIZE];
1273 volatile uint16_t u16_txFifo4Head = 0;
1274 volatile uint16_t u16_txFifo4Tail = 0;
1283 u16_tmp = u16_txFifo4Head;
1285 if (u16_tmp == UART4_TX_FIFO_SIZE) u16_tmp = 0;
1286 while (u16_tmp == u16_txFifo4Tail)
1289 au8_txFifo4[u16_tmp] = u8_c;
1290 u16_txFifo4Head = u16_tmp;
1294 void _ISR _U4TXInterrupt (
void) {
1295 if (u16_txFifo4Head == u16_txFifo4Tail) {
1301 if (u16_txFifo4Tail == UART4_TX_FIFO_SIZE)
1302 u16_txFifo4Tail = 0;
1305 U4TXREG = au8_txFifo4[u16_txFifo4Tail];
1317 while (IS_TRANSMIT_BUFFER_FULL_UART4())
1323 #ifdef UART4_RX_INTERRUPT
1325 # ifndef UART4_RX_FIFO_SIZE
1326 # define UART4_RX_FIFO_SIZE 32 //choose a size
1329 # ifndef UART4_RX_INTERRUPT_PRIORITY
1330 # define UART4_RX_INTERRUPT_PRIORITY 1
1333 volatile uint8_t au8_rxFifo4[UART4_RX_FIFO_SIZE];
1334 volatile uint16_t u16_rxFifo4Head = 0;
1335 volatile uint16_t u16_rxFifo4Tail = 0;
1341 return(u16_rxFifo4Head != u16_rxFifo4Tail);
1349 while (u16_rxFifo4Head == u16_rxFifo4Tail)
1352 if (u16_rxFifo4Tail == UART4_RX_FIFO_SIZE) u16_rxFifo4Tail=0;
1353 return au8_rxFifo4[u16_rxFifo4Tail];
1356 void _ISR _U4RXInterrupt (
void) {
1360 checkRxErrorUART4();
1363 if (u16_rxFifo4Head == UART4_RX_FIFO_SIZE)
1364 u16_rxFifo4Head = 0;
1365 if (u16_rxFifo4Head == u16_rxFifo4Tail) {
1369 au8_rxFifo4[u16_rxFifo4Head] = u8_c;
1377 return(IS_CHAR_READY_UART4());
1388 while (!IS_CHAR_READY_UART4())
1390 checkRxErrorUART4();
1397 #endif // # ifndef BOOTLOADER
1398 #if !defined(BOOTLOADER) || (DEFAULT_UART == 4)
1403 #ifndef DEFAULT_BRGH4
1404 # define DEFAULT_BRGH4 DEFAULT_BRGH
1407 #if (DEFAULT_BRGH4 != 0) && (DEFAULT_BRGH4 != 1)
1408 # error "Invalid value specified for DEFAULT_BRGH4."
1420 void configUART4(uint32_t u32_baudRate) {
1426 #if (HARDWARE_PLATFORM == EXPLORER16_100P) || (HARDWARE_PLATFORM == HARDMAPPED_UART)
1432 # if (HARDWARE_PLATFORM == DANGEROUS_WEB)
1433 # warning Building configUART4() for the Dangerous Web target.
1438 # elif (HARDWARE_PLATFORM == STARTER_BOARD_28P)
1439 # warning Building configUART4() for the StarterBoard_28P target.
1444 # elif (HARDWARE_PLATFORM == DEFAULT_DESIGN) || (HARDWARE_PLATFORM == MICROSTICK2)
1449 # elif (HARDWARE_PLATFORM == EMBEDDED_C1)
1450 # warning Building configUART4() for the Rev.C1 Embedded Systems target.
1455 # elif (HARDWARE_PLATFORM == EMBEDDED_F14)
1456 # warning Building configUART4() for the Rev.F14 Embedded Systems target.
1462 # error "Unknown hardware platform."
1465 # warning "UART4 pin mappings not defined. See comments below for more info."
1480 U4MODE = (0u << 15);
1501 (DEFAULT_BRGH4 << 3) |
1514 #
if (defined(__dsPIC33E__) || defined(__PIC24E__))
1531 ASSERT(u32_baudRate >= 1000L);
1540 while (U4STAbits.PERR || U4STAbits.FERR) {
1545 #ifdef UART4_RX_INTERRUPT
1547 _U4RXIP = UART4_RX_INTERRUPT_PRIORITY;
1550 #ifdef UART4_TX_INTERRUPT
1552 _U4TXIP = UART4_TX_INTERRUPT_PRIORITY;
1558 #endif // #if !defined(BOOTLOADER) || (DEFAULT_UART == 4)
1560 #endif // #if (NUM_UARTS >= 4)