33 #if (NUM_ECAN_MODS >= 1)
46 #ifndef ECAN_1TIME_CODE_DEFS
57 p_ecanmsg->w0.IDE = 0;
58 p_ecanmsg->w0.SRR = 0;
59 p_ecanmsg->w0.SID = u16_id;
60 p_ecanmsg->w1.EID17_6 = 0;
61 p_ecanmsg->w2.EID5_0 = 0;
62 p_ecanmsg->w2.RTR = 0;
63 p_ecanmsg->w2.RB1 = 0;
64 p_ecanmsg->w2.RB0 = 0;
65 p_ecanmsg->w2.DLC = u8_len;
78 p_ecanmsg->w0.IDE = 1;
79 p_ecanmsg->w0.SRR = 0;
80 p_ecanmsg->w0.SID = (u32_id >> 18) & 0x7FF;
81 p_ecanmsg->w1.EID17_6 = (u32_id >> 6) & 0xFFF;
82 p_ecanmsg->w2.EID5_0 = u32_id & 0x3F;
83 p_ecanmsg->w2.RTR = 0;
84 p_ecanmsg->w2.RB1 = 0;
85 p_ecanmsg->w2.RB0 = 0;
86 p_ecanmsg->w2.DLC = u8_len;
96 uint32_t u32_id, u32_tmp;
97 u32_tmp = p_ecanmsg->w0.SID;
98 u32_id = u32_tmp << 18;
99 u32_tmp = p_ecanmsg->w1.EID17_6;
100 u32_id = u32_id | (u32_tmp << 6) | p_ecanmsg->w2.EID5_0;
104 #define ECAN_1TIME_CODE_DEFS
119 C1CTRL1bits.CANCKS = ECAN_FCAN_IS_FP;
122 #if FCY == GET_FCY(FRCPLL_FCY40MHz) // <- This needs to be reverified! - rnn13
130 C1CFG2 = ECAN_NO_WAKEUP |
133 ECAN_SEG2_PROGRAMMABLE |
137 C1CFG1 = ECAN_SYNC_JUMP_4 |
140 #elif FCY == GET_FCY(FRCPLL_FCY60MHz)
156 C1CFG2 = ECAN_NO_WAKEUP |
159 ECAN_SEG2_PROGRAMMABLE |
163 C1CFG1 = ECAN_SYNC_JUMP_4 |
166 #warning "ECAN module not configured for current processor frequency! Edit function configECAN1()."
178 if (u8_bufNum > 15) {
179 u8_bufNum = u8_bufNum - 16;
180 C1RXFUL2 = C1RXFUL2 & ~(1<<u8_bufNum);
182 C1RXFUL1 = C1RXFUL1 & ~(1<<u8_bufNum);
193 if (u8_bufNum > 15) {
194 u8_bufNum = u8_bufNum - 16;
195 return(C1RXFUL2 & (1<<u8_bufNum));
197 return(C1RXFUL1 & (1<<u8_bufNum));
221 C1TR01CONbits.TXEN0 = u8_type;
222 C1TR01CONbits.TX0PRI = u8_priority;
225 C1TR01CONbits.TXEN1 = u8_type;
226 C1TR01CONbits.TX1PRI = u8_priority;
229 C1TR23CONbits.TXEN2 = u8_type;
230 C1TR23CONbits.TX2PRI = u8_priority;
233 C1TR23CONbits.TXEN3 = u8_type;
234 C1TR23CONbits.TX3PRI = u8_priority;
237 C1TR45CONbits.TXEN4 = u8_type;
238 C1TR45CONbits.TX4PRI = u8_priority;
241 C1TR45CONbits.TXEN5 = u8_type;
242 C1TR45CONbits.TX5PRI = u8_priority;
245 C1TR67CONbits.TXEN6 = u8_type;
246 C1TR67CONbits.TX6PRI = u8_priority;
249 C1TR67CONbits.TXEN7 = u8_type;
250 C1TR67CONbits.TX7PRI = u8_priority;
263 C1TR01CONbits.TXREQ0 = 1;
266 C1TR01CONbits.TXREQ1 = 1;
269 C1TR23CONbits.TXREQ2 = 1;
272 C1TR23CONbits.TXREQ3 = 1;
275 C1TR45CONbits.TXREQ4 = 1;;
278 C1TR45CONbits.TXREQ5 = 1;
281 C1TR67CONbits.TXREQ6 = 1;
284 C1TR67CONbits.TXREQ7 = 1;
297 return(C1TR01CONbits.TXREQ0);
299 return(C1TR01CONbits.TXREQ1);
301 return(C1TR23CONbits.TXREQ2);
303 return(C1TR23CONbits.TXREQ3);
305 return(C1TR45CONbits.TXREQ4);
307 return(C1TR45CONbits.TXREQ5);
309 return(C1TR67CONbits.TXREQ6);
311 return(C1TR67CONbits.TXREQ7);
327 uint16_t *pu16_CxRXFySID,*pu16_CxRXFyEID, *pu16_CxFMSKSEL1, *pu16_CxBUFPNT1;
329 uint16_t u16_eid15_0;
330 uint16_t u16_eid17_16;
338 pu16_CxRXFySID = (uint16_t*) &C1RXF0SID + (u8_filtNum << 1);
339 pu16_CxRXFyEID = pu16_CxRXFySID + 1;
340 pu16_CxFMSKSEL1 = (uint16_t*) &C1FMSKSEL1 + (u8_filtNum >> 3);
341 pu16_CxBUFPNT1 = (uint16_t*) &C1BUFPNT1 + (u8_filtNum >> 2);
347 u16_sid = (u32_id >> 18) & 0x7FF;
348 u16_eid17_16 = (u32_id >>16) & 0x3;
349 u16_eid15_0 = u32_id & 0xFFFF;
350 *pu16_CxRXFySID =(u16_sid <<5) | ECAN_MATCH_EID | u16_eid17_16;
351 *pu16_CxRXFyEID = u16_eid15_0;
353 u16_sid = u32_id & 0x7FF;
354 *pu16_CxRXFySID = u16_sid <<5;
359 u8_startPos = 4 * (u8_filtNum & 0x3);
360 u16_mask = ~ ( 0xF << u8_startPos);
361 *pu16_CxBUFPNT1 = (*pu16_CxBUFPNT1 & u16_mask) | (u8_bufnum << u8_startPos);
364 u8_startPos = 2 * (u8_filtNum & 0x7);
365 u16_mask = ~ ( 0x3 << u8_startPos);
366 *pu16_CxFMSKSEL1 = (*pu16_CxFMSKSEL1 & u16_mask) | (u8_maskReg << u8_startPos);
368 C1FEN1 = C1FEN1 | (1 << u8_filtNum) ;
385 uint16_t *pu16_CxRXMySID,*pu16_CxRXMyEID;
387 uint16_t u16_meid15_0;
388 uint16_t u16_meid17_16;
390 pu16_CxRXMySID =(uint16_t*) &C1RXM0SID + (u8_maskNum << 1);
391 pu16_CxRXMyEID = pu16_CxRXMySID + 1;
397 u16_msid = (u32_idMask >> 18) & 0x7FF;
398 u16_meid17_16 = (u32_idMask >>16) & 0x3;
399 u16_meid15_0 = u32_idMask & 0xFFFF;
400 if (u8_matchType) *pu16_CxRXMySID =(u16_msid <<5) | ECAN_MATCH_EID | u16_meid17_16;
401 else *pu16_CxRXMySID =(u16_msid <<5) | u16_meid17_16;
402 *pu16_CxRXMyEID = u16_meid15_0;
404 u16_msid = u32_idMask & 0x7FF;
405 if (u8_matchType) *pu16_CxRXMySID = (u16_msid <<5) | ECAN_MATCH_EID ;
406 else *pu16_CxRXMySID = (u16_msid <<5);
412 #endif // #if (NUM_ECAN_MODS >= ${x})
450 #if (NUM_ECAN_MODS >= 2)
463 #ifndef ECAN_1TIME_CODE_DEFS
474 p_ecanmsg->w0.IDE = 0;
475 p_ecanmsg->w0.SRR = 0;
476 p_ecanmsg->w0.SID = u16_id;
477 p_ecanmsg->w1.EID17_6 = 0;
478 p_ecanmsg->w2.EID5_0 = 0;
479 p_ecanmsg->w2.RTR = 0;
480 p_ecanmsg->w2.RB1 = 0;
481 p_ecanmsg->w2.RB0 = 0;
482 p_ecanmsg->w2.DLC = u8_len;
495 p_ecanmsg->w0.IDE = 1;
496 p_ecanmsg->w0.SRR = 0;
497 p_ecanmsg->w0.SID = (u32_id >> 18) & 0x7FF;
498 p_ecanmsg->w1.EID17_6 = (u32_id >> 6) & 0xFFF;
499 p_ecanmsg->w2.EID5_0 = u32_id & 0x3F;
500 p_ecanmsg->w2.RTR = 0;
501 p_ecanmsg->w2.RB1 = 0;
502 p_ecanmsg->w2.RB0 = 0;
503 p_ecanmsg->w2.DLC = u8_len;
513 uint32_t u32_id, u32_tmp;
514 u32_tmp = p_ecanmsg->w0.SID;
515 u32_id = u32_tmp << 18;
516 u32_tmp = p_ecanmsg->w1.EID17_6;
517 u32_id = u32_id | (u32_tmp << 6) | p_ecanmsg->w2.EID5_0;
521 #define ECAN_1TIME_CODE_DEFS
529 void configBaudECAN2(
void) {
536 C2CTRL1bits.CANCKS = ECAN_FCAN_IS_FP;
539 #if FCY == GET_FCY(FRCPLL_FCY40MHz) // <- This needs to be reverified! - rnn13
547 C2CFG2 = ECAN_NO_WAKEUP |
550 ECAN_SEG2_PROGRAMMABLE |
554 C2CFG1 = ECAN_SYNC_JUMP_4 |
557 #elif FCY == GET_FCY(FRCPLL_FCY60MHz)
573 C2CFG2 = ECAN_NO_WAKEUP |
576 ECAN_SEG2_PROGRAMMABLE |
580 C2CFG1 = ECAN_SYNC_JUMP_4 |
583 #warning "ECAN module not configured for current processor frequency! Edit function configECAN1()."
593 void clrRxFullFlagECAN2(
uint8_t u8_bufNum) {
595 if (u8_bufNum > 15) {
596 u8_bufNum = u8_bufNum - 16;
597 C2RXFUL2 = C2RXFUL2 & ~(1<<u8_bufNum);
599 C2RXFUL1 = C2RXFUL1 & ~(1<<u8_bufNum);
610 if (u8_bufNum > 15) {
611 u8_bufNum = u8_bufNum - 16;
612 return(C2RXFUL2 & (1<<u8_bufNum));
614 return(C2RXFUL1 & (1<<u8_bufNum));
621 void clrRxFullOvfFlagsECAN2(
void) {
638 C2TR01CONbits.TXEN0 = u8_type;
639 C2TR01CONbits.TX0PRI = u8_priority;
642 C2TR01CONbits.TXEN1 = u8_type;
643 C2TR01CONbits.TX1PRI = u8_priority;
646 C2TR23CONbits.TXEN2 = u8_type;
647 C2TR23CONbits.TX2PRI = u8_priority;
650 C2TR23CONbits.TXEN3 = u8_type;
651 C2TR23CONbits.TX3PRI = u8_priority;
654 C2TR45CONbits.TXEN4 = u8_type;
655 C2TR45CONbits.TX4PRI = u8_priority;
658 C2TR45CONbits.TXEN5 = u8_type;
659 C2TR45CONbits.TX5PRI = u8_priority;
662 C2TR67CONbits.TXEN6 = u8_type;
663 C2TR67CONbits.TX6PRI = u8_priority;
666 C2TR67CONbits.TXEN7 = u8_type;
667 C2TR67CONbits.TX7PRI = u8_priority;
676 void startTxECAN2(
uint8_t u8_bufNum) {
680 C2TR01CONbits.TXREQ0 = 1;
683 C2TR01CONbits.TXREQ1 = 1;
686 C2TR23CONbits.TXREQ2 = 1;
689 C2TR23CONbits.TXREQ3 = 1;
692 C2TR45CONbits.TXREQ4 = 1;;
695 C2TR45CONbits.TXREQ5 = 1;
698 C2TR67CONbits.TXREQ6 = 1;
701 C2TR67CONbits.TXREQ7 = 1;
714 return(C2TR01CONbits.TXREQ0);
716 return(C2TR01CONbits.TXREQ1);
718 return(C2TR23CONbits.TXREQ2);
720 return(C2TR23CONbits.TXREQ3);
722 return(C2TR45CONbits.TXREQ4);
724 return(C2TR45CONbits.TXREQ5);
726 return(C2TR67CONbits.TXREQ6);
728 return(C2TR67CONbits.TXREQ7);
744 uint16_t *pu16_CxRXFySID,*pu16_CxRXFyEID, *pu16_CxFMSKSEL1, *pu16_CxBUFPNT1;
746 uint16_t u16_eid15_0;
747 uint16_t u16_eid17_16;
755 pu16_CxRXFySID = (uint16_t*) &C2RXF0SID + (u8_filtNum << 1);
756 pu16_CxRXFyEID = pu16_CxRXFySID + 1;
757 pu16_CxFMSKSEL1 = (uint16_t*) &C2FMSKSEL1 + (u8_filtNum >> 3);
758 pu16_CxBUFPNT1 = (uint16_t*) &C2BUFPNT1 + (u8_filtNum >> 2);
764 u16_sid = (u32_id >> 18) & 0x7FF;
765 u16_eid17_16 = (u32_id >>16) & 0x3;
766 u16_eid15_0 = u32_id & 0xFFFF;
767 *pu16_CxRXFySID =(u16_sid <<5) | ECAN_MATCH_EID | u16_eid17_16;
768 *pu16_CxRXFyEID = u16_eid15_0;
770 u16_sid = u32_id & 0x7FF;
771 *pu16_CxRXFySID = u16_sid <<5;
776 u8_startPos = 4 * (u8_filtNum & 0x3);
777 u16_mask = ~ ( 0xF << u8_startPos);
778 *pu16_CxBUFPNT1 = (*pu16_CxBUFPNT1 & u16_mask) | (u8_bufnum << u8_startPos);
781 u8_startPos = 2 * (u8_filtNum & 0x7);
782 u16_mask = ~ ( 0x3 << u8_startPos);
783 *pu16_CxFMSKSEL1 = (*pu16_CxFMSKSEL1 & u16_mask) | (u8_maskReg << u8_startPos);
785 C2FEN1 = C2FEN1 | (1 << u8_filtNum) ;
801 void configRxMaskECAN2(
uint8_t u8_maskNum, uint32_t u32_idMask,
uint8_t u8_idType,
uint8_t u8_matchType) {
802 uint16_t *pu16_CxRXMySID,*pu16_CxRXMyEID;
804 uint16_t u16_meid15_0;
805 uint16_t u16_meid17_16;
807 pu16_CxRXMySID =(uint16_t*) &C2RXM0SID + (u8_maskNum << 1);
808 pu16_CxRXMyEID = pu16_CxRXMySID + 1;
814 u16_msid = (u32_idMask >> 18) & 0x7FF;
815 u16_meid17_16 = (u32_idMask >>16) & 0x3;
816 u16_meid15_0 = u32_idMask & 0xFFFF;
817 if (u8_matchType) *pu16_CxRXMySID =(u16_msid <<5) | ECAN_MATCH_EID | u16_meid17_16;
818 else *pu16_CxRXMySID =(u16_msid <<5) | u16_meid17_16;
819 *pu16_CxRXMyEID = u16_meid15_0;
821 u16_msid = u32_idMask & 0x7FF;
822 if (u8_matchType) *pu16_CxRXMySID = (u16_msid <<5) | ECAN_MATCH_EID ;
823 else *pu16_CxRXMySID = (u16_msid <<5);
829 #endif // #if (NUM_ECAN_MODS >= ${x})